NSBMC096VF-25

Overview

The NSBMC096VF-25 is a burst memory controller designed for high-performance systems utilizing the i960 CA/CF SuperScalar Embedded Processor. It implements all aspects of DRAM control, translating the processor's burst access protocol to the page mode access protocol supported by dynamic RAMs. The device manages one or two-way interleaved arrangements of DRAMs, allowing data read or write at the rate of one word per system clock cycle during burst access. It supports DRAM densities from 256 kB to 64 MB and operates within a supply voltage range of 4.5 V to 5.5 V.

Feature Summary

• Interfaces directly to the i960 CA/CF processor without requiring glue logic.
• Integrates page cache management to optimize DRAM access efficiency.
• Manages page mode dynamic memory devices in non-interleaved or two-way interleaved configurations.
• Includes on-chip memory address multiplexers/drivers and a 24-bit heartbeat timer.

Applications

• High-performance embedded systems using i960 CA/CF processors
• Memory subsystems requiring direct translation between burst protocols and DRAM page modes
• Systems utilizing interleaved DRAM arrangements for sustained throughput

Procurement Notes

Verify component authenticity through authorized distributors or manufacturer channels. Confirm package integrity and pin alignment with the 132-pin PQFP specification. Review datasheet SNOS687A for absolute maximum ratings and recommended operating conditions before integration. Ensure proper power plane design to support switching characteristics.

Selection Notes

Select this controller when designing systems based on the i960 CA/CF architecture that require efficient DRAM management. Consider its capability to handle DRAM sizes up to 64 MB and support for both interleaved and non-interleaved memory banks. Evaluate the need for integrated page cache management and bus watch timers to simplify system design and reduce external logic requirements.

Part Context

The NSBMC096 series addresses the memory control challenges posed by high instruction rates in i960 CA/CF processors. It serves as a functional equivalent to the V96BMC, providing a cost-effective alternative to static RAM by enabling high-density dynamic RAM usage. The controller reduces design complexity and space requirements while maintaining performance through optimized burst access handling.

Replacement Considerations

The NSBMC096VF-25 is marked as obsolete. Direct replacement options may include the standard NSBMC096BM variant if available, though availability is limited. Designers should evaluate legacy inventory or consider architectural migration strategies given the discontinued status of this specific part number.