PEB 20532 F V1.3

Telecom Overview

The Infineon PEB 20532 is a dual-channel Serial Optimized Communication Controller (SEROCCO-M) designed for datacom applications. It integrates two independent SCCs with FIFO buffers, a Baud Rate Generator, and clock recovery via DPLL. The device supports multiple protocol modes including HDLC/SDLC, PPP, Asynchronous, BISYNC, LAPB/LAPD, and SS7. It features a flexible microprocessor interface compatible with Intel and Motorola bus standards, external DMA support, and general-purpose I/O pins. The component operates within specified DC and AC electrical limits and utilizes a P-TQFP-100-3 package.

Telecom Feature Summary

• Supports diverse communication protocols such as HDLC, SDLC, PPP, Asynchronous, BISYNC, LAPB/LAPD, and Signaling System #7.
• Integrates dual Serial Communication Controllers with dedicated transmit and receive FIFOs for efficient data handling.
• Provides flexible clocking options through a Baud Rate Generator and Digital Phase-Locked Loop for clock recovery.
• Features a versatile microprocessor interface supporting both Intel and Motorola bus architectures.

Telecom Applications

• Datacom system integration
• Point-to-point serial configurations
• Multipoint bus configurations

Telecom Procurement Notes

Verify the specific version suffix against the official datasheet to ensure compatibility with required signal multiplexing corrections and register definitions. Confirm that the procurement channel provides documentation for the exact revision level, as updates regarding OSR/CD and OST/CTS signals were implemented in later revisions.

Telecom Selection Notes

Select this controller when designing systems requiring dual-channel serial optimization with hardware protocol offloading. Ensure the host processor supports the required bus interface timing and that the application benefits from integrated FIFO management and automatic CRC generation. Evaluate thermal characteristics relative to the P-TQFP-100-3 package constraints.

Telecom Part Context

The PEB 20532 belongs to the SEROCCO-M family, representing an evolution of the ESCC serial core with specific enhancements and simplifications. It serves as a specialized communication controller distinct from general-purpose UARTs by offering extensive Layer-2 protocol processing capabilities directly in hardware.

Telecom Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Engineering changes may require validation of pinout compatibility and register mapping differences if considering alternative controllers.

Telecom FAQ

How does the PEB 20532 handle clock recovery?

The device incorporates a Digital Phase-Locked Loop (DPLL) algorithm to recover clocks from incoming data streams, supporting various encoding schemes like NRZ, NRZI, FM0, FM1, and Manchester.

What bus interfaces are supported by the microprocessor connection?

The PEB 20532 supports both Intel and Motorola bus interface timings, allowing flexibility in connecting to different types of host processors or microcontrollers.

Does the controller support full-duplex LAPB operation?

Yes, the device includes procedural support for Full-Duplex LAPB/LAPD operation as part of its Layer-2 functional capabilities.