SI5346B-D-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5346B-D-GM is a dual DSPLL jitter attenuator in a 44-QFN package. It provides four inputs and four outputs with any-frequency conversion capabilities. The device supports differential output frequencies up to 350 MHz and LVCMOS outputs up to 250 MHz. Input frequency ranges include differential signals from 8 kHz to 750 MHz and LVCMOS from 8 kHz to 250 MHz. It operates on a 1.8 V core voltage (±5%) and features ultra-low jitter of 95 fs typ. The component includes non-volatile memory for configuration storage.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable flexible routing of any input clock to any output clock via a programmable crosspoint.
• Supports automatic and manual hitless input switching, including ramped transitions and glitchless frequency changes.
• Integrates fault monitoring for Loss of Signal (LOS), Out of Frequency (OOF), and Loss of Lock (LOL) with interrupt capabilities.
• Features in-circuit programmable non-volatile memory allowing the device to power up in a known configuration.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type and temperature range. Ensure compatibility with ClockBuilder Pro software for configuration. Check for RoHS-6 compliance status. Confirm availability through authorized distributors as supply levels may vary. Validate that the selected part number matches the required output frequency range specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when a dual DSPLL architecture with four inputs and four outputs is required. Verify that the maximum output frequency requirement does not exceed 350 MHz for differential outputs. Ensure the application can accommodate the 44-QFN 7x7 mm package dimensions. Confirm that the serial interface requirements align with I2C or SPI protocols supported by the device.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5346 family, which utilizes fourth-generation DSPLL technology. It serves as the dual-PLL counterpart to the quad-PLL Si5347 series. Both families share similar functional blocks but differ in integration density and package size. The Si5346 offers a smaller form factor suitable for space-constrained designs requiring high-performance jitter attenuation.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5346A-D-GM: Offers higher output frequency range up to 720 MHz compared to the 350 MHz limit of the Si5346B variant. Other Si5346 variants include C and D grades with different performance characteristics. Cross-referencing with the Si5347 series requires accounting for the additional PLLs and increased pin count.