SI5362B-A15684-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5362B-A15684-GM is a jitter attenuator and clock multiplier from the Si536x family, manufactured by Skyworks Solutions. It features two integrated DSPLLs and zero MultiSynths, housed in a 72-lead QFN package (10 x 10 mm). The device supports up to 18 differential or 36 single-ended outputs with frequencies reaching 1.3 GHz via integer dividers. It accepts differential inputs from 8 kHz to 1 GHz and LVCMOS inputs up to 250 MHz. Operating conditions range from -40 °C to +95 °C ambient temperature. Supply voltages include 3.3 V for core and XO pins, and programmable 3.3 V, 2.5 V, or 1.8 V for outputs.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrates two independent DSPLLs for flexible clock generation without MultiSynths
• Delivers ultra-low phase jitter performance suitable for high-speed SerDes applications
• Supports enhanced hitless switching to minimize output phase transients during input clock changes
• Configurable via serial interface with non-volatile memory for power-up configuration

Clock Generators, PLLs, Frequency Synthesizers Applications

• 56G/112G/224G PAM4 SerDes clocking
• OTN muxponders and transponders
• 100/200/400/600/800G networking line cards
• Datacenter switches

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix A15684 against the manufacturer's current documentation to confirm factory-programmed frequency plans and interface settings. Ensure compatibility with the required SPI or I2C communication standards. Confirm that the 72-QFN package dimensions align with the target PCB layout constraints. Validate thermal management requirements given the maximum junction temperature limits under full load conditions.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when two independent PLL loops are required for separate clock domains without the need for fractional synthesis MultiSynths. Compare against the Si5361A if a single PLL with two MultiSynths is sufficient for the design. Consider the Si5363 if three independent PLLs are necessary. Ensure the application does not require output frequencies exceeding 1.3 GHz on integer dividers, as the Si5361H variant supports higher frequencies.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5361/Si5362/Si5363 family of jitter attenuators. The Si5362 variant specifically distinguishes itself by providing two DSPLLs and no MultiSynths, unlike the Si5361 which has one DSPLL and two MultiSynths. This architecture suits designs requiring multiple independent clock sources derived from different reference inputs or loop bandwidths.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5362A-Axxxxx-GM variants offer similar functionality but may differ in factory programming. Si5361A-Axxxxx-GM provides one DSPLL and two MultiSynths instead of two DSPLLs.