SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The SiZ346DT-T1-GE3 is a dual N-channel 30 V (D-S) MOSFET from Vishay Siliconix, utilizing TrenchFET Gen IV technology. It features an asymmetric PowerPAIR 3 x 3 leadless package with two independent channels. Channel-1 has a maximum RDS(on) of 28.5 mΩ at VGS = 10 V and a continuous drain current of 17 A. Channel-2 offers lower resistance at 11.5 mΩ max with a 30 A rating. The device supports a gate-source voltage range of ±20 V for Channel-1 and +20/-16 V for Channel-2, operates within -55 °C to +150 °C, and includes 100% UIS testing.
Verify the specific ordering suffix against official documentation to confirm compliance attributes such as halogen-free status. Ensure that the PowerPAIR package handling requirements are met during assembly, particularly regarding the exposed copper terminals. Confirm thermal management strategies align with the specified junction-to-ambient and junction-to-case resistance ratings for the intended operating environment.
Select this component when space-constrained designs require dual synchronous rectification or independent channel control within a 3 mm by 3 mm footprint. The asymmetric channel ratings allow designers to pair a high-current path with a lower-resistance auxiliary path. Verify that the required gate drive voltage levels match the specified thresholds for optimal on-state performance and switching efficiency.
This part belongs to the SiZ series of Vishay Siliconix MOSFETs, specifically designed for high-density power applications. It utilizes the PowerPAIR leadless package family, which eliminates traditional leads to reduce parasitic inductance and improve thermal dissipation capabilities compared to standard surface-mount packages.
Direct pin-compatible replacements must be sourced from official Vishay cross-reference lists. Verify that any substitute maintains the 30 V drain-source voltage rating and fits the PowerPAIR 3 x 3 outline dimensions. Ensure thermal resistance and gate charge specifications meet or exceed the original design requirements.