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Product Detailed Parameters
- Description：JFET 2N-CH 25V TO78-6
- Series：-
- Mfr：Vishay Siliconix
- Package：Tube
- FET Type：2 N-Channel (Dual)
- Voltage - Breakdown (V(BR)GSS)：25 V
- Drain to Source Voltage (Vdss)：-
- Current - Drain (Idss) @ Vds (Vgs=0)：12 mA @ 10 V
- Current Drain (Id) - Max：-
- Voltage - Cutoff (VGS off) @ Id：1 V @ 1 nA
- Input Capacitance (Ciss) (Max) @ Vds：5pF @ 10V
- Resistance - RDS(On)：-
- Power - Max：500 mW
- Operating Temperature：-55°C ~ 150°C (TJ)
- Mounting Type：Surface Mount
- Package / Case：TO-78-6 Metal Can
- Supplier Device Package：TO-78-6
- Grade：-
- Qualification：-
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Overview
The U430 is a matched N-channel JFET pair in a TO-78 package. It features a gate-source cutoff voltage (VGS(off)) range of -1 V to -4 V and a minimum breakdown voltage of -25 V. The device provides a minimum forward transconductance (gfs) of 10 mS and typical gate leakage of 15 pA. Differential gate-source voltage matching is typically 25 mV, with a common-mode rejection ratio of 75 dB. Operating junction temperature ranges from -55 °C to 150 °C.
Feature Summary
- Two-chip design providing tight differential matching for current, transconductance, and gate-source voltage.
- High slew rate and wideband performance suitable for frequencies beyond 250 MHz.
- Low offset and drift voltage characteristics minimize input error requirements.
- Low gate leakage current ensures high system sensitivity and insignificant signal loss.
Applications
- Wideband differential amplifiers
- High-speed comparators
- Impedance converters
Procurement Notes
Verify the specific lot traceability and military screening requirements if applicable, as the TO-78 package supports full military processing. Confirm that the selected units meet the required static and dynamic matching parameters defined in the datasheet tables. Ensure proper handling procedures are followed due to the ceramic package construction.
Selection Notes
Select the U430 when precise differential matching between two JFETs is critical for circuit accuracy. This component is appropriate for designs requiring low noise and high common-mode rejection. Consider the TO-78 package constraints and thermal derating requirements when designing the heat dissipation strategy for the application.
Part Context
The U430 belongs to a family of matched JFET pairs manufactured by Vishay Siliconix. It is designed to replace discrete matched pairs, ensuring consistent performance across production batches. The device utilizes silicon technology and is housed in a hermetic metal can package to protect against environmental factors.
Replacement Considerations
For similar products, refer to the low-noise U/SST401 series or the high-gain 2N5911/5912 devices. Consult the U421/423 data sheets for low-leakage alternatives. Verify pinout compatibility and electrical parameter overlaps before substituting other matched JFET pairs.
FAQ
What is the maximum power dissipation per side?
The maximum power dissipation is 300 mW per side, with a total device limit of 500 mW.
How does the U430 differ from the U431?
The U430 has a gate-source cutoff voltage range of -1 V to -4 V, while the U431 ranges from -2 V to -6 V.
What is the typical common-mode rejection ratio?
The typical common-mode rejection ratio (CMRR) is 75 dB.
