Z16C3220VSG1660

Overview

The Z16C3220VSG1660 is a multiprotocol serial communications controller manufactured by Zilog. It integrates dual-channel DMA with a high-speed serial channel to facilitate high data throughput. The device supports data rates up to 20 Mbit/sec and features two baud rate generators with a digital phase-locked loop for clock recovery. It includes 32-byte FIFOs for both receiver and transmitter operations. The IUSC™ supports asynchronous, HDLC/SDLC, byte-oriented synchronous, and transparent Bisync protocols. It offers a flexible bus interface compatible with 8 or 16-bit microprocessors, including the 680X0 and 8086 families. The component is housed in a 68-pin PLCC package.

Feature Summary

• Dual-channel DMA with 32-bit addressing and support for single buffer, pipelined, array-chained, and linked-list transfer modes.
• Multiprotocol operation supporting asynchronous, HDLC/SDLC, byte-oriented synchronous, and transparent Bisync formats under program control.
• Integrated digital phase-locked loop and dual baud rate generators for full-duplex communication up to 20 Mbit/sec.
• Flexible bus interface configurable for 8 or 16-bit data widths, directly supporting 680X0 and 8086 family bus interfaces.

Applications

• ISDN, T1, and E1 (CEPT) applications utilizing receive and transmit time slot assigners.
• High-throughput data communications systems requiring reduced CPU overhead via automated frame status and control transfers.
• Systems requiring direct connection to CISC and RISC processors such as Intel, Motorola, and Zilog families.

Procurement Notes

Verify the specific suffix 'VSG1660' against official Zilog documentation to confirm temperature range and package variations. Confirm RoHS compliance status as earlier revisions may not meet current standards. Check for obsolescence notices or product change notifications from the manufacturer before finalizing procurement plans.

Selection Notes

Select this component when system requirements demand integrated serial protocol handling and high-speed DMA capabilities within a single chip. Ensure the host processor bus interface matches the configurable 8 or 16-bit width options. Verify that the required protocols, such as HDLC or Bisync, are supported by the software drivers available from Zilog.

Part Context

The Z16C32 belongs to the IUSC™ (Integrated Universal Serial Controller) family developed by Zilog. This series was designed to replace discrete serial and DMA controllers, reducing board space and component count. The Z16C32 specifically targets applications needing versatile serial communication with efficient memory management through its on-chip DMA channels.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided source material. Consult Zilog technical support for legacy replacement options or cross-reference with other multiprotocol serial controllers if discontinuation is confirmed.