AT17LV010A-10PI

Overview

The AT17LV010A-10PI is a 1-Mbit (1,048,576-bit) serial EEPROM configurator designed for FPGA configuration. It operates at 3.3V or 5.0V with an access time of 10ns. The device supports In-System Programming via a 2-wire bus and features low-power CMOS technology. It is housed in an 8-lead PDIP package and functions as a master serial configurator for SRAM-based FPGAs.

Feature Summary

• Provides non-volatile storage for FPGA configuration programs
• Supports In-System Programming through a simple 2-wire serial interface
• Enables cascading capabilities to support higher-density arrays
• Allows user-programmable reset polarity for system compatibility

Applications

• Configuration of Altera FLEX and APEX FPGAs
• Configuration of Xilinx XC3000, XC4000, and Spartan devices
• Configuration of Lucent ORCA and Motorola MPA1000 FPGAs
• Emulation of Atmel AT24CXXX serial EEPROMs

Procurement Notes

Verify the specific voltage grade and temperature range required for your application, as commercial and industrial variants exist. Confirm that the 8-lead PDIP package aligns with your PCB footprint requirements. Ensure programming equipment supports the 2-wire serial interface for ISP operations if in-system updates are planned.

Selection Notes

Select this component when a 1-Mbit capacity is needed for single or cascaded FPGA configurations. Consider the 3.3V or 5.0V supply options based on the target FPGA's voltage levels. The 8-lead PDIP package is suitable for through-hole mounting or prototyping where space constraints allow.

Part Context

This part belongs to the AT17A series of FPGA configuration EEPROMs from Microchip Technology (formerly Atmel). These devices are specialized memory solutions intended to store bitstreams for programmable logic devices. The series offers various densities ranging from 64-Kbit to 2-Mbit, with the AT17LV010A representing the 1-Mbit tier.

Replacement Considerations

AT17LV010A-10PC

FAQ

How does the device handle cascading for larger configurations?

The nCASC output goes Low when the address counter reaches its maximum value, disabling the DATA line driver. This signal can drive the nCS input of the next configurator in a daisy-chain, allowing subsequent devices to clock out data.

What is the function of the RESET/OE pin?

The RESET/OE pin controls the tri-state buffer on the DATA output and enables the address counter. A Low level resets the counter, while a High level enables data output. Its logic polarity is programmable by the user during programming.