BLD6G21LS-50,112

Overview

The BLD6G21LS-50 is a fully integrated Doherty transistor utilizing GEN6 LDMOS technology, designed for TD-SCDMA base station applications between 2010 MHz and 2025 MHz. It integrates main and peak devices with an input splitter and output combiner in a single SOT1130B package. Key electrical parameters include a drain-source voltage of 65 V, typical average output power of 8 W, and power gain of 14.5 dB at 28 V supply. Drain efficiency reaches 43% under 6-carrier TD-SCDMA conditions with 10.8 dB PAR. The device features independent bias control for the peak amplifier down to 0 V.

Feature Summary

• Fully integrated Doherty solution combining main and peak amplifiers with internal matching networks
• Optimized asymmetrical power splitter and power combiner for simplified circuit design
• Independent bias control capability allowing peak amplifier operation down to 0 V gate-source voltage
• High ruggedness capable of withstanding 10:1 VSWR mismatch across all phases

Applications

• TD-SCDMA multi-carrier base station power amplifiers
• High efficiency RF power amplifiers requiring digital pre-distortion
• Applications operating within the 2010 MHz to 2025 MHz frequency range

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current catalog to confirm the package variant. The 'S' suffix indicates the earless flanged ceramic package (SOT1130B), distinct from the standard flanged version. Confirm RoHS compliance status and moisture sensitivity handling requirements prior to assembly to ensure component integrity during manufacturing processes.

Selection Notes

Select this component for designs requiring a compact, fully integrated Doherty architecture without external matching components for the internal structure. Ensure the application operates within the specified 2010 MHz to 2025 MHz band. Verify that the thermal management system can handle the junction-to-case thermal resistance of 2.1 K/W while maintaining the case temperature at or below 80°C for optimal performance and reliability.

Part Context

This device belongs to Ampleon's GEN6 LDMOS family, specifically engineered for high-efficiency linear amplification in wireless infrastructure. It represents a consolidation of discrete Doherty components into a single monolithic chip, reducing board space and simplifying the impedance matching network requirements for base station transmitters.

Replacement Considerations

The BLD6G21L-50 serves as the primary alternative, differing only by its flanged ceramic package (SOT1130A) which includes mounting holes, whereas the BLD6G21LS-50 uses the earless SOT1130B package.