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The Nexperia BSS138BKS is a dual N-channel enhancement mode Field-Effect Transistor utilizing Trench MOSFET technology within a SOT363 (SC-88) plastic surface-mounted package. It features a drain-source voltage of 60 V and a continuous drain current of 320 mA per transistor at 25 °C. The device exhibits a typical drain-source on-state resistance of 1.6 Ω at VGS = 10 V and ID = 320 mA. Gate-source voltage limits are ±20 V, with a threshold voltage typically ranging from 0.48 V to 1.1 V. Total power dissipation reaches 445 mW per device at 25 °C ambient temperature.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging configuration and reel specifications. Ensure the component matches the required automotive qualification status if deployed in vehicle systems. Cross-reference the marking code LG% with manufacturing site codes to validate authenticity and traceability during incoming inspection processes.
Select this component when space-constrained designs require dual N-channel functionality in a minimal footprint. The low threshold voltage supports efficient drive from 1.8 V or 3.3 V logic families. Verify thermal management capabilities against the junction-to-ambient resistance values provided in the datasheet for the intended PCB copper area and duty cycle constraints.
This device belongs to the BSS138 family of small-signal MOSFETs produced by Nexperia. It represents the dual-channel variant housed in the SOT363 package, distinct from single-channel counterparts like the BSS138BK found in SOT23 packages. The series utilizes trench technology to optimize switching speed and on-resistance performance relative to planar alternatives.
NX138BKS
The device provides electrostatic discharge protection up to 1.5 kV when tested according to the Human Body Model (HBM) standard.
The gate-source threshold voltage decreases as the junction temperature increases, exhibiting negative temperature coefficient behavior typical of MOSFETs.
Yes, the component is qualified in accordance with the AEC-Q101 stress test qualification standard for discrete semiconductors.