DMP3021SPDW-13

$0.29

Description：MOSFET 2P-CH 30V 10A PWRDI50
Series：-

SKU:2d5c096a0eab Category: FET, MOSFET Arrays Brand: Diodes Incorporated

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Product introduction

Product Detailed Parameters

Description：MOSFET 2P-CH 30V 10A PWRDI50
Series：-
Mfr：Diodes Incorporated
Package：Bulk
Technology：MOSFET (Metal Oxide)
Configuration：2 P-Channel
FET Feature：-
Drain to Source Voltage (Vdss)：30V
Current - Continuous Drain (Id) @ 25°C：10A (Ta), 39A (Tc)
Rds On (Max) @ Id, Vgs：18mOhm @ 8A, 10V
Vgs(th) (Max) @ Id：2.5V @ 250µA
Gate Charge (Qg) (Max) @ Vgs：34nC @ 10V
Input Capacitance (Ciss) (Max) @ Vds：1799pF @ 15V
Power - Max：4.7W (Ta)
Operating Temperature：-55°C ~ 150°C (TJ)
Mounting Type：Surface Mount
Package / Case：8-PowerTDFN
Supplier Device Package：PowerDI5060-8 (Type UXD)
Grade：-
Qualification：-

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DMP3021SPDW-13

Overview

The DMP3021SPDW-13 is a dual p-channel enhancement mode MOSFET in a PowerDI5060-8 package. It features a -30V drain-source voltage rating and low on-resistance of 18mΩ at VGS=-10V and 28mΩ at VGS=-5V. The device supports continuous drain currents up to -39A at case temperature +70°C. Operating temperatures range from -55°C to +150°C. Key electrical parameters include a gate threshold voltage of -1.0V to -2.5V, input capacitance of 1799pF, and total gate charge of 34nC at VGS=-10V.

Feature Summary

Dual P-Channel Enhancement Mode MOSFET configuration
Low RDS(on) for minimized on-state losses
Wettable flank design for improved optical inspection
ESD protected gate structure

Applications

Wireless charging systems
DC-DC converters
Power management circuits

Procurement Notes

Verify the specific ordering suffix '-13' corresponds to the 2500-unit tape and reel carrier type as documented. Confirm that the component meets RoHS 3 and Halogen-free requirements if environmental compliance is mandatory for the target assembly process. Ensure the selected variant matches the required thermal and electrical specifications for the intended application environment.

Selection Notes

Select this component for applications requiring high-efficiency power management with low conduction losses. The dual channel architecture allows for compact designs in space-constrained environments. Evaluate the thermal resistance characteristics against the expected ambient temperature conditions to ensure reliable operation within the specified junction temperature limits.

Part Context

This part belongs to Diodes Incorporated's portfolio of power management solutions. It utilizes the PowerDI5060-8/SWP (Type UXD) package, which provides thermally efficient performance. The device is designed to minimize on-state resistance while maintaining superior switching performance for modern electronic systems.