MMFTN620KD-AQ

FET, MOSFET Arrays Overview

The MMFTN620KD-AQ is a dual N-channel enhancement mode FET in a SOT-26 package. It features a drain-source voltage of 60 V and a DC drain current of 350 mA per device. The on-state resistance is less than 1.5 Ω at VGS = 4.5 V and ID = 250 mA, or 2.25 Ω at VGS = 10 V and ID = 500 mA. Peak drain current reaches 1.0 A for pulses under 100 µs. Total power dissipation is 500 mW with a junction temperature range of -55°C to +150°C. Input capacitance is typically 35 pF, and total gate charge is 1.3 nC.

FET, MOSFET Arrays Feature Summary

• Dual FET configuration within a single compact surface-mount package
• ESD protected gate structure for enhanced signal integrity
• AEC-Q101 qualification compliant suffix for automotive applications

FET, MOSFET Arrays Applications

• Signal processing circuits
• Logic level converters
• Driver stages

FET, MOSFET Arrays Procurement Notes

Verify the specific ordering suffix when purchasing. The standard version lacks automotive certification, while the -Q suffix indicates AEC-Q101 compliance and the -AQ suffix denotes qualification status. Confirm RoHS and REACH compliance requirements match your manufacturing standards before finalizing orders.

FET, MOSFET Arrays Selection Notes

Select this component for low-voltage switching tasks requiring dual channels in minimal space. Ensure the gate drive voltage meets the threshold requirements for the desired on-resistance. Verify that the thermal management strategy accommodates the specified thermal resistance to ambient value under expected load conditions.

FET, MOSFET Arrays Part Context

This part belongs to Diotec's portfolio of small-signal MOSFETs designed for commercial and industrial use. The dual configuration allows designers to consolidate multiple switching functions into a single footprint, reducing board space compared to using individual discrete transistors.

FET, MOSFET Arrays Replacement Considerations

No official substitutes are listed by the manufacturer. Cross-compatibility requires verifying pinout alignment, voltage ratings, and package dimensions against existing designs.