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Product Detailed Parameters
- Description：MOSFET 2N-CH 30V 5A 8TSSOP
- Series：TrenchMOS™
- Mfr：NXP USA Inc.
- Package：Tape & Reel (TR)
- Technology：MOSFET (Metal Oxide)
- Configuration：2 N-Channel (Dual)
- FET Feature：Logic Level Gate
- Drain to Source Voltage (Vdss)：30V
- Current - Continuous Drain (Id) @ 25°C：5A
- Rds On (Max) @ Id, Vgs：33mOhm @ 3.5A, 4.5V
- Vgs(th) (Max) @ Id：700mV @ 1mA
- Gate Charge (Qg) (Max) @ Vgs：28nC @ 5V
- Input Capacitance (Ciss) (Max) @ Vds：1478pF @ 10V
- Power - Max：2.3W
- Operating Temperature：-55°C ~ 150°C (TJ)
- Mounting Type：Surface Mount
- Package / Case：8-TSSOP (0.173", 4.40mm Width)
- Supplier Device Package：8-TSSOP
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Overview
The PMWD30UN is a dual N-channel enhancement mode field-effect transistor utilizing μTrenchMOS technology. It provides two independent channels in an SOT530-1 (TSSOP8) plastic package. Key electrical parameters include a drain-source voltage of 30 V, continuous drain current up to 5 A at 25 °C, and peak drain current of 18 A. The on-state resistance is typically 30 mΩ at VGS = 4.5 V and ID = 3.5 A. Total power dissipation is rated at 2.3 W at 25 °C. Gate charge is typically 28 nC, with input capacitance of 1478 pF.
Feature Summary
- Dual channel configuration using TrenchMOS technology for low profile surface mounting
- Very low threshold voltage enabling fast switching performance
- High current handling capability with low on-state resistance
Applications
- Portable appliances
- PCMCIA cards
- Battery management systems
- Load switching circuits
Procurement Notes
Verify the specific manufacturer origin as the datasheet references Philips Semiconductors while the brand is listed as NXP USA Inc. Confirm the package type matches the SOT530-1 outline. Check for any Customer Product/Process Change Notifications regarding design updates or availability status changes since the original publication date.
Selection Notes
Select this component for applications requiring dual N-channel MOSFETs in a compact thin shrink small outline package. Ensure the operating junction temperature remains within the -55 °C to +150 °C range. Verify that the gate drive voltage meets the requirements for the specified on-state resistance values, particularly for low voltage logic levels.
Part Context
This device belongs to the μTrenchMOS family of ultra-low level FETs designed for efficient power switching in space-constrained environments. The dual configuration allows for synchronized control or bridge topologies within a single footprint, reducing board area compared to discrete single-channel alternatives.
Replacement Considerations
Consult official replacement lists for equivalent dual N-channel MOSFETs in SOT530-1 packages. Verify pinout compatibility and thermal characteristics before substitution.
FAQ
What is the maximum peak drain current?
The peak drain current is 18 A under pulsed conditions with a pulse width of 10 μs or less.
How does the on-state resistance vary with temperature?
The on-state resistance increases with junction temperature; it rises from a typical 30 mΩ at 25 °C to 56 mΩ at 150 °C.
What is the reverse recovery time of the source-drain diode?
The reverse recovery time is typically 50 ns when sourcing 4 A with a di/dt of -100 A/μs.
