XC18V256SO20C

Overview

The XC18V256SO20C is a 3.3V in-system programmable configuration PROM from the XC18V00 series, manufactured by Xilinx (now AMD). It provides 262,144 bits of non-volatile storage for FPGA bitstreams. The device supports serial and parallel configuration modes with access times up to 20ns. It features 5V tolerant I/Os, JTAG compliance, and an endurance of 20,000 program/erase cycles. The component is housed in a 20-pin SOIC package.

Feature Summary

• Supports in-system programming via IEEE 1149.1 JTAG interface
• Enables cascading through Chip Enable Output for expanded memory capacity
• Provides data security options to inhibit unauthorized reading via JTAG
• Features 5V tolerant inputs compatible with mixed voltage systems

Applications

• Configuration of Xilinx Virtex-II FPGAs
• Configuration of Xilinx Spartan-IIE FPGAs
• Configuration of Xilinx Virtex-E FPGAs

Procurement Notes

Verify that the ordering suffix 'SO20' corresponds to the 20-pin Small Outline Integrated Circuit package. Confirm the device revision matches the required specifications. Ensure compatibility with the target FPGA's configuration mode pins. Check for lead-free status if RoHS compliance is mandatory for the assembly process.

Selection Notes

Select this device when a 256-Kbit configuration memory is sufficient for the target FPGA design. Choose the SO20 package for applications requiring a small footprint on the PCB. Consider the XC18V00 series for designs needing in-system reprogrammability and JTAG-based testing capabilities without external volatile memory controllers.

Part Context

This component belongs to the XC18V00 series of in-system programmable configuration PROMs. These devices are designed specifically to store and provide configuration data to Xilinx FPGAs and CPLDs. The series includes various densities ranging from 256-Kbit to 4-Mbit, offering flexibility for different FPGA sizes.

Replacement Considerations

XC18V256VQG44C

FAQ

How is the CF pin function handled in the 20-pin package?

The 20-pin packages do not have a dedicated CF pin. The CF function can be routed to pin 7 using the CF --> D4 setting, provided the parallel output mode is not used.

What is the maximum number of program/erase cycles supported?

The device guarantees an endurance level of 20,000 in-system program/erase cycles.