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AD9644CCPZRL7-80 is listed in the Analog To Digital Converters (ADC) range at ChipApex. The manufacturer field lists Analog Devices Inc.. Its product description is IC ADC 14BIT PIPELINED 48LFCSP. Review the specifications below when checking this part for your BOM.
The AD9644CCPZRL7-80 is a dual-channel, 14-bit analog-to-digital converter (ADC) operating at an 80 MSPS sampling rate. It features JESD204A coded serial digital outputs and operates from a single 1.8 V supply. The device utilizes a multistage differential pipelined architecture with integrated output error correction logic. Key specifications include a signal-to-noise ratio (SNR) of 70.0 dBFS at 70 MHz input frequency and 80 MSPS sampling rate. Power consumption is rated at 423 mW at the maximum sample rate. The component is housed in a 48-lead LFCSP package and supports industrial temperature ranges.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the reel packaging designation and speed grade. Ensure that the procurement channel provides valid traceability for the Analog Devices Inc. part number. Cross-reference the component marking with the datasheet revision history to validate authenticity and production batch details before integration into manufacturing processes.
Select this model when a dual-channel 14-bit resolution is required alongside high-speed serial output capabilities via JESD204A. Consider the 80 MSPS conversion rate and 70.0 dBFS SNR specification for intermediate frequency sampling applications. Evaluate the 423 mW power dissipation against system thermal constraints and verify compatibility with the 1.8 V supply voltage requirements for both analog and digital domains.
This component belongs to the AD9644 series of high-speed analog-to-digital converters manufactured by Analog Devices Inc. The series is designed for communications applications requiring high performance combined with low cost and small size. The AD9644 family supports sampling speeds of either 80 MSPS or 155 MSPS, utilizing a multistage differential pipelined architecture with integrated output error correction logic.
Public confirmed substitute part numbers are not available in the provided source material.
The SNR is 70.0 dBFS at an input frequency of 70 MHz and a sampling rate of 80 MSPS.
The device integrates an on-chip PLL that multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock, allowing users to provide a single ADC sampling clock.
The power consumption is 423 mW at 80 MSPS with a sine wave input.
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