AD9680BCPZ-1000

Analog To Digital Converters (ADC) Overview

The AD9680BCPZ-1000 is a dual-channel, 14-bit analog-to-digital converter (ADC) operating at a maximum sampling rate of 1 GSPS. It features a multistage differential pipelined architecture with integrated output error correction logic and on-chip buffers. The device supports flexible input ranges from 1.46 V p-p to 1.94 V p-p and includes programmable termination impedances of 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential. Key performance metrics include a signal-to-noise ratio (SNR) of 67.2 dBFS at 10 MHz input frequency and a spurious-free dynamic range (SFDR) of 88 dBFS at the same frequency. It utilizes JESD204B Subclass 1 coded serial digital outputs and operates with supply voltages of 1.25 V, 2.5 V, and 3.3 V.

Analog To Digital Converters (ADC) Feature Summary

• Integrated digital downconverters (DDCs) featuring 12-bit numerically controlled oscillators and cascaded half-band decimation filters for efficient signal processing.
• Programmable fast overrange detection mechanism that monitors incoming signal power to facilitate automatic gain control implementation.
• Flexible JESD204B interface supporting one-, two-, or four-lane configurations with deterministic latency capabilities.
• On-chip voltage reference and buffered inputs designed to simplify system design and reduce external component count.

Analog To Digital Converters (ADC) Applications

• Diversity multiband, multimode digital receivers
• General-purpose software radios
• Ultrawideband satellite receivers
• Signals intelligence (SIGINT)
• DOCSIS 3.0 CMTS upstream receive paths

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific speed grade suffix matches the required sampling rate, as the AD9680 series includes variants up to 1.25 GSPS. Confirm package type is LFCSP-64 and check RoHS compliance status. Ensure the ordering part number corresponds exactly to the 1 GSPS specification to avoid functional mismatches in high-speed data acquisition systems.

Analog To Digital Converters (ADC) Selection Notes

Select this component when a dual-channel ADC with 14-bit resolution and 1 GSPS throughput is required. Consider the integrated DDCs if baseband processing is needed to reduce downstream FPGA load. Evaluate the 2 GHz full-power bandwidth against the highest expected input signal frequency. Verify that the available supply rails match the 1.25 V, 2.5 V, and 3.3 V requirements specified in the datasheet.

Analog To Digital Converters (ADC) Part Context

The AD9680BCPZ-1000 belongs to the AD9680 family of high-speed dual ADCs from Analog Devices. This family offers pin-compatible variants with different maximum sampling rates, including 1.25 GSPS, 820 MSPS, and 500 MSPS. All variants share the same 64-lead LFCSP package and core architecture, allowing for design flexibility across different bandwidth applications while maintaining consistent board layout.

Analog To Digital Converters (ADC) Replacement Considerations

AD9680BCPZ-1250: Higher sampling rate variant (1.25 GSPS). Pin-compatible but requires verification of thermal and power constraints. AD9680BCPZ-820: Lower sampling rate variant (820 MSPS). Pin-compatible. AD9680BCPZ-500: Lowest sampling rate variant (500 MSPS). Pin-compatible.