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The DMC3061SVTQ-13 is a complementary pair enhancement mode MOSFET manufactured by Diodes Incorporated. It integrates an N-channel and a P-channel device within a single TSOT26 package. The N-channel transistor provides a drain-source voltage of 30V, with on-resistance values of 60mΩ at VGS=10V and 100mΩ at VGS=4.5V. Continuous drain currents reach 3.4A at 25°C for the N-channel and -2.7A for the P-channel. The P-channel unit exhibits on-resistances of 95mΩ at VGS=-10V and 140mΩ at VGS=-4.5V. Power dissipation is rated at 0.88W to 1.08W depending on mounting conditions.
Verify the specific ordering suffix against official documentation before procurement. The suffix '-13' indicates a tape and reel quantity of 10,000 units, whereas '-7' denotes 3,000 units per reel. Confirm that the required packaging format aligns with automated assembly equipment specifications. Ensure compliance with RoHS directives and automotive quality requirements if applicable to the target deployment environment.
Select this component when space-constrained designs require matched N-channel and P-channel switching capabilities. Evaluate thermal constraints carefully, as power dissipation ratings depend heavily on PCB copper area and substrate thickness. Verify gate drive voltages match the specified thresholds for optimal on-resistance performance. Consider the TSOT26 package dimensions during layout planning to ensure adequate pad spacing and thermal relief.
This part belongs to the DMC3061SVTQ series of complementary MOSFETs from Diodes Incorporated. It serves as a specialized solution for synchronous rectification and high-efficiency power conversion tasks. The integrated design reduces board footprint compared to discrete dual-transistor implementations while maintaining matched electrical characteristics for balanced switching behavior.
Direct replacements include the DMC3061SVT-7 variant, which shares identical electrical specifications but utilizes a 3,000-unit tape and reel packaging format. Both parts maintain the same TSOT26 mechanical outline and pinout configuration.