EMD28164PCH-60-SU

Memory IC Overview

The EMD28164PCH-60-SU is a 128Mb Mobile DDR SDRAM fabricated using high-performance CMOS technology. It features a x16 data width and operates with VDD/VDDQ supply voltages between 1.7V and 1.95V. The device supports clock rates of 200MHz, 166MHz, and 133MHz. It utilizes a double data rate architecture with four internal banks for concurrent operation. Key specifications include CAS latencies of 2 and 3, burst lengths of 2, 4, 8, and 16, and a 64ms refresh period. The interface uses LVCMOS signaling.

Memory IC Feature Summary

• Supports Partial Array Self-Refresh (PASR) and Auto Temperature Compensated Self-Refresh (ATCSR).
• Includes Power Down Mode, Deep Power Down Mode, and Clock Stop capability during idle periods.
• Features programmable output buffer driver strength and Data Mask (DM) for write data.
• Utilizes differential clock inputs (CK and CK) and bidirectional data strobes (DQS).

Memory IC Applications

• High bandwidth memory system applications requiring high performance.
• Mobile devices utilizing synchronous double data rate Dynamic RAM.
• Systems requiring low standby power consumption through various power-down modes.

Memory IC Procurement Notes

Verify the specific speed grade suffix matches the required operating frequency (200MHz, 166MHz, or 133MHz) as indicated in the part number structure. Confirm that the package type corresponds to the 60-ball FPBGA assignment detailed in the datasheet. Ensure compatibility with the specified 1.7V to 1.95V operating voltage range for both core and I/O supplies.

Memory IC Selection Notes

Select this component for designs requiring a 128Mb capacity with a x16 interface width. Consider the available CAS latency options of 2 and 3 based on timing requirements. Evaluate the need for PASR and ATCSR features if power management during self-refresh is critical. Ensure the system supports the initialization sequence involving two auto-refresh commands before normal operation.

Memory IC Part Context

This device belongs to the Mobile DDR SDRAM family, designed for mobile and high-performance applications. It employs a 2n-prefetch architecture to achieve high-speed data transfer at the I/O balls. The organization consists of four banks, each containing 33,554,432 bits arranged as 4,096 rows by 512 columns by 16 bits.

Memory IC Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

Memory IC FAQ

What is the initialization sequence required for the EMD28164PCH-60-SU?

The device requires power-up, stable clocks, a PRECHARGE ALL command, two AUTO REFRESH commands, and programming of both the Mode Register and Extended Mode Register before it is ready for valid commands.

How does the Data Mask (DM) function work?

DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS.