EPC2111

FET, MOSFET Arrays Overview

The EPC2111 is an enhancement-mode Gallium Nitride (eGaN) power transistor configured as a half-bridge. It integrates two lateral GaN FETs, Q1 and Q2, on a single die measuring 3.5 x 1.5 mm. The device features a continuous drain-to-source voltage of 30 V and operates with a junction temperature range of –40 to 150 °C. Q1 exhibits a typical on-resistance of 19 mΩ, while Q2 demonstrates a lower typical on-resistance of 8 mΩ. Both transistors support a continuous drain current of 16 A at 25°C ambient temperature. The component is supplied in passivated die form with solder bumps, designed for high-frequency switching applications up to 10 MHz.

FET, MOSFET Arrays Feature Summary

• Integration of two distinct eGaN FETs (Q1 and Q2) within a single half-bridge configuration to minimize parasitic inductance.
• Lateral device structure providing exceptionally low gate charge and zero reverse recovery charge for efficient high-speed switching.
• Passivated die form factor with solder bumps, enabling high-density footprint implementation in compact power modules.
• Negative temperature coefficient for on-resistance, allowing stable parallel operation and robust thermal performance.

FET, MOSFET Arrays Applications

• High frequency DC-DC converters
• Point-of-load (POL) converter architectures
• High density power supply designs requiring minimal footprint

FET, MOSFET Arrays Procurement Notes

Verify the specific lot date code and die orientation markings upon receipt, as the component is supplied as a bare die in tape and reel format. Ensure handling procedures comply with electrostatic discharge (ESD) protocols suitable for passivated semiconductor dies. Confirm that assembly equipment supports the required 4mm pitch stencil printing and reflow profiles for SAC305 solder bumps to maintain electrical integrity.

FET, MOSFET Arrays Selection Notes

Select this component when designing half-bridge topologies requiring operation above 1 MHz. Choose Q1 for standard switching legs where moderate on-resistance is acceptable, or Q2 for paths demanding lower conduction losses due to its reduced RDS(on). Ensure the gate drive circuit accommodates the specified 5 V logic level and negative off-state recommendation. Validate thermal management strategies against the provided junction-to-board resistance values for the target PCB copper area.

FET, MOSFET Arrays Part Context

The EPC2111 belongs to the Efficient Power Conversion Corporation eGaN family of lateral gallium nitride transistors. Unlike vertical MOSFETs, these devices utilize a lateral structure that eliminates body diode reverse recovery issues. This specific model consolidates a complementary pair of switches into one die, simplifying layout and reducing loop inductance compared to discrete solutions. It represents a shift toward monolithic integration in wide-bandgap power electronics.

FET, MOSFET Arrays Replacement Considerations

No official direct substitute part numbers are listed in the datasheet. When evaluating alternatives, ensure the replacement maintains the 30 V rating and compatible gate threshold characteristics. Verify that any cross-reference offers similar die dimensions for land pattern compatibility or requires significant PCB redesign. Discrete GaN FETs may require external bootstrap circuits and careful dead-time management not inherent to this integrated half-bridge.

FET, MOSFET Arrays FAQ

What is the recommended gate-off voltage for the EPC2111?

EPC recommends using 0 V for the OFF state. Applying a negative gate drive voltage increases the reverse drain-source voltage, which may exceed safe operating limits if not carefully managed.

How does the on-resistance of Q2 compare to Q1?

Q2 has a significantly lower typical on-resistance of 8 mΩ compared to Q1's 19 mΩ. This asymmetry allows designers to optimize specific legs of a converter for lower conduction losses.

Is the EPC2111 available in a standard surface-mount package?

No, the EPC2111 is supplied only in passivated die form with solder bumps. It requires direct mounting onto a PCB using a custom land pattern and stencil printing process.