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FDC6036P is listed in the FET, MOSFET Arrays range at ChipApex. The manufacturer field lists onsemi. Its product description is MOSFET 2P-CH 20V 5A SSOT6. Review the specifications below when checking this part for your BOM.
FET, MOSFET Arrays specifications for FDC6036P
- Description：MOSFET 2P-CH 20V 5A SSOT6
- Series：PowerTrench®
- Mfr：onsemi
- Package：Tape & Reel (TR),Cut Tape (CT)
- Technology：MOSFET (Metal Oxide)
- Configuration：2 P-Channel (Dual)
- FET Feature：Logic Level Gate
- Drain to Source Voltage (Vdss)：20V
- Current - Continuous Drain (Id) @ 25°C：5A
- Rds On (Max) @ Id, Vgs：44mOhm @ 5A, 4.5V
- Vgs(th) (Max) @ Id：1.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs：14nC @ 4.5V
- Input Capacitance (Ciss) (Max) @ Vds：992pF @ 10V
- Power - Max：900mW
- Operating Temperature：-55°C ~ 150°C (TJ)
- Mounting Type：Surface Mount
- Package / Case：6-SSOT Flat-lead, SuperSOT™-6 FLMP
- Supplier Device Package：SuperSOT™-6
- Grade：-
- Qualification：-
FET, MOSFET Arrays datasheet and documents for FDC6036P
FET, MOSFET Arrays Overview
The FDC6036P is a dual P-Channel MOSFET utilizing PowerTrench technology, designed for battery power management. It features a FLMP SSOT-6 package with bottom drain contact for enhanced thermal performance. Key electrical parameters include a Drain-Source Voltage (VDSS) of -20 V and continuous Drain Current (ID) of -5 A at 25°C. The device specifies RDS(ON) values of 44 mΩ @ VGS = -4.5 V, 64 mΩ @ VGS = -2.5 V, and 95 mΩ @ VGS = -1.8 V. Total Gate Charge (Qg) is typically 10 nC. Operating junction temperature ranges from -55°C to +150°C.
FET, MOSFET Arrays Feature Summary
- Dual P-Channel configuration optimized for low voltage applications
- PowerTrench process ensures extremely low on-resistance
- FLMP SSOT-6 package provides enhanced thermal dissipation in standard footprint
FET, MOSFET Arrays Applications
- Battery management systems
- Charger applications
- Load switching circuits
FET, MOSFET Arrays Procurement Notes
Verify the component status as Obsolete within the Fairchild Semiconductor product lifecycle. Confirm that the FLMP SSOT-6 package marking corresponds to the specific revision C2 datasheet documentation. Ensure compatibility with existing board layouts due to the bottom drain contact design.
FET, MOSFET Arrays Selection Notes
Select this component for low-voltage dual-channel switching where space efficiency is critical. Evaluate the gate threshold voltage specifications against the available drive voltages in the target circuit. Consider the thermal resistance characteristics when designing the copper pad layout for adequate heat dissipation.
FET, MOSFET Arrays Part Context
This part belongs to the PowerTrench family developed by Fairchild Semiconductor, which is now part of onsemi. The series focuses on low-voltage enhancement mode MOSFETs. The FLMP SSOT-6 packaging allows for high-density surface mount assembly while maintaining robust thermal handling capabilities for portable electronics.
FET, MOSFET Arrays Replacement Considerations
Publicly confirmed substitute part numbers are not provided in the source material.
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