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The MIXA10WB1200TED is a silicon-based IGBT module manufactured by IXYS, belonging to the MIXA series utilizing XPT technology. It features a three-phase inverter configuration housed in an E2-Pack screw-mount package. The device supports a maximum collector-emitter voltage of 1.2 kV and operates within a temperature range of -40°C to +125°C. Electrical characteristics include a continuous collector current of 10 A at 25°C and a saturation voltage of 1.8 V. Power dissipation ratings are specified as 60 W for the inverter leg and 100 W for the brake leg. The module incorporates integrated freewheeling diodes and is designed for robust performance in industrial power conversion applications.
Verify component authenticity through authorized IXYS distributors or certified suppliers. Confirm RoHS compliance status and check for specific REACH SVHC declarations relevant to your region. Ensure the ordering suffix matches the required pinout and packaging specifications. Request original manufacturer documentation to validate technical parameters before integration into production designs.
Select this module for applications requiring a compact three-phase solution with integrated braking capability. Compare the 10 A current rating against load requirements to ensure adequate margin. Evaluate the E2-Pack thermal resistance against your heatsink design to maintain junction temperatures within the specified limits during peak operation cycles.
This component is part of the IXYS MIXA family of six-pack IGBT modules. It shares the XPT technology platform with variants like the MIXA30W1200TED but differs in current handling capacity and specific internal configuration for three-phase inverter and brake circuits. The MIXA series is widely recognized for its reliability in medium-power industrial applications.
Direct replacements within the same series include the MIXA10WB1200TML. Cross-brand equivalents require careful verification of pin compatibility, thermal characteristics, and electrical ratings to ensure functional parity without circuit redesign.