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The MRFX600HR5 is a wideband RF power LDMOS transistor from NXP Semiconductors, housed in the NI-780H-4L package. It operates across 1.8 to 400 MHz with a maximum drain-source voltage of 179 Vdc and a total device dissipation of 1333 W at 25°C case temperature. The component delivers up to 680 W CW output power at 87.5–108 MHz with 21.3 dB gain and 83% efficiency, or 600 W peak pulse power at 230 MHz with 26.4 dB gain. It features integrated ESD protection and supports single-ended or push-pull configurations.
Verify the specific ordering suffix R5 confirms the reel packaging configuration containing 50 units on a 13-inch reel with 56 mm tape width. Confirm the NI-780H-4L package designation matches the required screw-mount thermal interface. Ensure compatibility with the intended biasing network given the 65 Vdd maximum rating and quiescent current requirements.
Select this component for designs requiring high power density across a wide bandwidth without complex impedance matching networks. The unmatched input and output simplify circuit layout compared to matched counterparts. Consider the thermal resistance characteristics when designing heat sinks for continuous wave operations versus pulsed duty cycles.
This device belongs to the MRFX600H family of high ruggedness lateral MOSFETs designed for demanding RF environments. The family includes variants such as MRFX600HS and MRFX600GS, which share similar electrical performance but differ in package style and mounting configuration. The MRFX600HR5 specifically denotes the reel-packaged version of the standard NI-780H-4L device.
Direct replacements within the same family include MRFX600HSR5 and MRFX600GSR5, provided the package form factor aligns with the mechanical constraints of the application.
The maximum operating junction temperature range extends up to +225 °C.
The transistor is qualified to withstand VSWR ratios greater than 65:1 at all phase angles with 3 dB overdrive without experiencing device degradation.
Yes, the device is suitable for linear applications provided appropriate biasing is implemented to manage the gate threshold voltage and quiescent current.