AD9250BCPZRL7-170

Overview

The AD9250BCPZRL7-170 is a dual-channel, 14-bit analog-to-digital converter (ADC) from Analog Devices Inc. It supports sampling rates up to 170 MSPS and features JESD204B serial digital outputs compliant with Subclass 0 or Subclass 1 standards. The device operates on a single 1.8 V supply and includes an internal voltage reference. Key electrical specifications include a signal-to-noise ratio of 70.6 dBFS at 185 MHz input frequency and 250 MSPS, and a spurious-free dynamic range of 88 dBc under the same conditions. Total power consumption is 711 mW at maximum speed.

Feature Summary

• Integrates two 14-bit ADC cores with a multistage differential pipelined architecture and output error correction logic.
• Features a configurable JESD204B output block supporting data rates up to 5 Gbps per lane via CML outputs.
• Includes an on-chip phase-locked loop (PLL) to multiply the ADC sampling clock for generating the JESD204B data rate clock.
• Supports flexible analog input ranges from 1.4 V p-p to 2.0 V p-p with an integrated voltage reference.

Applications

• Multimode digital receivers including TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, and LTE.
• DOCSIS 3.0 CMTS upstream receive paths and HFC digital reverse path receivers.
• Radar receivers and COMSEC radio architectures.
• General-purpose software radios and broadband data applications.

Procurement Notes

Verify the specific ordering suffix RL7 against the manufacturer's current documentation to confirm reel packaging and tape-and-reel specifications. Ensure compatibility with the required JESD204B link parameters and SPI configuration settings before finalizing procurement orders.

Selection Notes

Select this component for designs requiring high-speed dual-channel conversion with deterministic latency via JESD204B Subclass 1 support. Consider the 1.8 V single-supply operation and integrated reference when designing power rails. Verify that the receiving FPGA or ASIC supports the required CML input levels and lane configurations.

Part Context

This part belongs to the AD9250 family of high-performance dual-channel ADCs. It shares architectural similarities with the AD9250-250 variant but is specified for a maximum conversion rate of 170 MSPS. Both variants utilize the same 48-lead LFCSP package and interface protocols.

Replacement Considerations

The AD9250BCPZRL7-250 is a functional substitute within the same family offering higher sampling speeds. Ensure that the system clock and JESD204B lane rates can accommodate the performance differences if substituting between speed grades.