CDCR83DBQR

Application Specific Clock/Timing Overview

The CDCR83DBQR is a Direct Rambus clock generator (DRCG) designed for Direct Rambus memory systems supporting 800-MHz data transfer rates. It synchronizes the Rambus channel clock with external system or processor clocks using an internal PLL and phase aligner. The device operates from a single 3.3-V supply, consuming approximately 120 mW at 300 MHz. It supports frequency multipliers of 4, 6, 8, and 16/3, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz. Cycle-cycle jitter is less than 50 ps at 400 MHz. Packaged in a 24-pin SSOP/QSOP (DBQ), it supports industrial temperature ranges of −40°C to 85°C.

Application Specific Clock/Timing Feature Summary

• Direct Rambus Clock Generator (DRCG) for 800-MHz data transfer rate systems
• Internal PLL with phase alignment logic to minimize skew between PCLKM and SYNCLKN
• Supports frequency multipliers: 4, 6, 8, and 16/3 via MULT0/MULT1 pins
• Cycle-cycle jitter less than 50 ps at 400 MHz
• Spread spectrum clocking tracking capability to reduce EMI

Application Specific Clock/Timing Applications

• Desktop, workstation, server, and mobile PC motherboards with Direct Rambus memory
• Systems requiring synchronization between Rambus channel clock and ASIC clock domains
• Applications utilizing TI’s 133-MHz clock synthesizers such as CDC924 and CDC921

Application Specific Clock/Timing Procurement Notes

Verify the marketing status before design inclusion, as the CDCR83 family is classified as NRND (Not Recommended for New Designs). Confirm that the DBQ package variant meets mechanical constraints. Ensure compatibility with existing system clock references (REFCLK) within the 33 MHz to 100 MHz range to maintain valid BUSCLK outputs between 267 MHz and 400 MHz.

Application Specific Clock/Timing Selection Notes

Select this component when designing Direct Rambus memory subsystems requiring precise phase alignment between the Rambus channel and system controllers. Verify that the input REFCLK frequency allows for the desired multiply ratio (4, 6, 8, or 16/3) to achieve target BUSCLK speeds. Ensure the application environment stays within the −40°C to 85°C operating temperature range and utilizes a stable 3.3-V supply.

Application Specific Clock/Timing Part Context

The CDCR83 is part of Texas Instruments' Direct Rambus clock generator family, specifically engineered for high-speed memory interfaces. It replaces discrete clock generation solutions by integrating PLL, multiplier, and phase alignment functions into a single 24-pin package. The device is designed to work in conjunction with memory controllers that divide PCLK and BUSCLK frequencies to synchronize communication domains without additional latency.

Application Specific Clock/Timing Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The device is marked as NRND; consult Texas Instruments for current availability or legacy support options.