SI5335D-B04972-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5335D-B04972-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer from Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports three independent pin-selectable configurations and features flexible output drivers capable of LVPECL, LVDS, CML, HCSL, CMOS, SSTL, or HSTL formats with independent voltage levels (1.5, 1.8, 2.5, or 3.3 V). It operates on a single core supply of 1.8, 2.5, or 3.3 V, with core currents of 45 mA in PLL mode and 12 mA in buffer mode. The component is housed in a 4x4 mm, 24-QFN package and functions within an ambient temperature range of –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent output banks supporting differential pairs or single-ended outputs with configurable logic families including LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL.
• Zero ppm frequency synthesis error across all outputs via patented MultiSynth technology, replacing multiple discrete clock sources.
• Three user-assignable, pin-selectable device configurations allowing one IC to replace up to three separate clock generators.
• Dual selectable PLL loop bandwidths (1.6 MHz or 475 kHz) for optimized jitter attenuation in PCIe and DSL applications.

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock generation and jitter attenuation
• Ethernet switch and router timing
• Processor and FPGA clocking systems
• DSLAM/PON and telecom line cards
• Broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific configuration parameters encoded in the B04972 suffix against the system requirements, as this part is factory-customized. Confirm that the required input reference frequency and output drive strengths match the pre-programmed settings. Ensure the PCB land pattern adheres to the recommended 24-QFN outline to maintain thermal performance and signal integrity.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when a design requires four distinct, non-integer-related clock frequencies from a single source with zero ppm error. Choose between the 1.6 MHz or 475 kHz loop bandwidth based on whether the application prioritizes wider jitter attenuation (1.6 MHz) or faster lock times/stability (475 kHz). Verify that the target output voltage levels (1.5V, 1.8V, 2.5V, or 3.3V) are compatible with the connected receivers.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5335 series serves as a high-flexibility replacement for traditional crystal oscillators and multiple clock buffers. The 'D' indicates a specific revision or variant within the family, while 'GMR' denotes the tape-and-reel packaging format. This model integrates the functionality of clock generation, buffering, and level translation into a compact form factor, simplifying board layout and reducing component count in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the Si5335?

The device supports output frequencies up to 350 MHz for LVPECL, LVDS, CML, SSTL, and HSTL formats. HCSL outputs are supported up to 250 MHz, and CMOS outputs up to 200 MHz.

How does the device handle frequency synthesis error?

Using Skyworks' patented MultiSynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of the configuration.

Can the Si5335 operate without an external crystal?

Yes, it supports multiple input types including external crystals (25 or 27 MHz), CMOS inputs (10–200 MHz), SSTL/HSTL inputs (10–350 MHz), and differential inputs (10–350 MHz).