SI5345B-B03701-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-B03701-GMR is a jitter attenuating clock multiplier from the Si5345 family, featuring four inputs and ten outputs in a 64-QFN package. It supports output frequencies up to 350 MHz with ultra-low jitter of 90 fs rms. The device utilizes fourth-generation DSPLL and MultiSynth technologies for any-frequency generation. Key electrical parameters include a differential input range of 8 kHz to 750 MHz and an LVCMOS input range of 8 kHz to 250 MHz. Output ranges are 100 Hz to 1028 MHz (differential) and 100 Hz to 250 MHz (LVCMOS). Operating voltage is VDD: 1.8 V ±5% and VDDA: 3.3 V ±5%. Temperature range is –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fractional and integer synthesis.
• Features programmable jitter attenuation bandwidth ranging from 0.1 Hz to 4 kHz for optimized performance.
• Supports hitless input clock switching between fractionally related clocks without phase offset propagation.
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the B03701 suffix against the target design requirements. Confirm that the QFN-64 package dimensions match the PCB land pattern. Ensure compatibility with the I2C or SPI serial interface used by the host controller. Check for RoHS compliance status if required by local regulations.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when output frequencies are limited to 350 MHz, as higher frequency variants exist within the Si5345 family. Verify that the required number of inputs (four) and outputs (ten) aligns with the system architecture. Consider the integrated loop filter benefits over discrete solutions for noise reduction. Use ClockBuilder Pro software to validate the specific jitter performance and holdover characteristics for the application.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D series of jitter attenuators. The 'B' designation indicates a maximum output frequency limit of 350 MHz, distinguishing it from the 'A' and 'C' variants which support up to 1028 MHz. The 'D' denotes the revision level of the datasheet and silicon. The 'GMR' suffix typically indicates tape and reel packaging for surface mount assembly.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

SI5345A-D-GMR offers higher frequency support up to 1028 MHz but requires verification of pinout and register compatibility. SI5345C-D-GMR provides integer-only synthesis at high frequencies. Ensure that any substitute maintains the same 64-QFN footprint and voltage specifications.