AD9680BCPZ-820

Analog To Digital Converters (ADC) Overview

The AD9680BCPZ-820 is a dual-channel, 14-bit analog-to-digital converter (ADC) from Analog Devices Inc., operating at a maximum sampling rate of 820 MSPS. It features JESD204B Subclass 1 coded serial digital outputs and a pipeline architecture with integrated output error correction logic. The device includes on-chip buffers, sample-and-hold circuits, and an internal voltage reference. Key electrical specifications include a full power bandwidth of 2 GHz, a signal-to-noise ratio (SNR) of 67.2 dBFS at 10 MHz input frequency, and an effective number of bits (ENOB) of 10.9 bits. Differential nonlinearity (DNL) is ±0.5 LSB, while integral nonlinearity (INL) is ±2.5 LSB. Power consumption is 2.9 W in default mode.

Analog To Digital Converters (ADC) Feature Summary

• Dual-channel 14-bit ADC cores with multistage differential pipelined architecture
• JESD204B Subclass 1 high-speed serialized digital outputs
• Integrated wideband digital downconverters (DDCs) with NCO and half-band filters
• Programmable fast overrange detection for efficient AGC implementation

Analog To Digital Converters (ADC) Applications

• Communications diversity multiband, multimode digital receivers
• General-purpose software radios
• Ultrawideband satellite receivers
• Radars and signals intelligence (SIGINT)
• DOCSIS 3.0 CMTS upstream receive paths

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific speed grade suffix to ensure the component matches the required 820 MSPS sampling rate specification. Confirm that the LFCSP-64 package orientation and pinout align with the target PCB layout design. Ensure the system power supply rails meet the strict voltage tolerances defined in the datasheet for AVDD1, AVDD2, and DVDD to maintain performance integrity.

Analog To Digital Converters (ADC) Selection Notes

Select this component when a dual-channel, 14-bit resolution is required alongside high-speed data conversion capabilities up to 820 MSPS. Consider the integrated DDCs if digital filtering or frequency translation is needed within the ADC to reduce downstream FPGA processing load. Evaluate the 2 GHz analog input bandwidth against the highest frequency components present in the signal chain to ensure adequate coverage without aliasing issues.

Analog To Digital Converters (ADC) Part Context

This part belongs to the AD9680 family, which offers multiple speed grades including 500 MSPS, 1 GSPS, and 1.25 GSPS variants. All members share the same 64-lead LFCSP package and functional block diagram, differing primarily in their maximum supported sampling rates and associated AC performance metrics. The BC suffix indicates a specific temperature and packaging variant within the broader product line.

Analog To Digital Converters (ADC) Replacement Considerations

AD9680BCPZ-1000

Analog To Digital Converters (ADC) FAQ

What is the nominal analog input voltage range for the AD9680-820?

The nominal differential input voltage range for the AD9680-820 is 1.70 V p-p.

Does the AD9680BCPZ-820 support simultaneous sampling?

Yes, the dual ADC cores feature simultaneous sampling capabilities as documented in the product highlights.

How many lanes can the JESD204B interface be configured for?

Users can configure the JESD204B interface in one-, two-, or four-lane configurations depending on the DDC settings and receiving logic requirements.