ADC09DJ800AAV

Analog To Digital Converters (ADC) Overview

The ADC09DJ800AAV is a dual-channel, 9-bit analog-to-digital converter operating at an 800 MSPS sampling rate. It features a non-interleaved architecture with internal dithering to reduce high-order harmonics. The device provides a full-scale input voltage of 800mVPP-DIFF and a full-power input bandwidth of 6GHz. Performance specifications include an SNR of 53.5dBFS and an ENOB of 8.51Bits at –1dBFS with a 97MHz input. It utilizes a JESD204C serial interface supporting up to 17.16Gbps baud-rate with 64B/66B and 8B/10B encoding modes. Power consumption is 555mW per channel at the maximum sampling rate.

Analog To Digital Converters (ADC) Feature Summary

• Non-interleaved architecture with integrated dither for harmonic reduction
• JESD204C interface with Subclass-1 support for deterministic latency
• Internal PLL and VCO for optional sampling clock generation
• Multiple clock outputs including SYSREF windowing and timestamp I/O

Analog To Digital Converters (ADC) Applications

• Light detection and ranging (LiDAR)
• Multi-channel oscilloscopes and digitizers
• Wireless communications test equipment
• Electronic warfare (SIGINT, ELINT)

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific AAV suffix against the manufacturer's current documentation to confirm package type and pinout compatibility. Ensure that the ordering information matches the exact dual-channel variant required for the design. Cross-reference the datasheet revision history to confirm the availability of the specific manufacturing lot or date code if traceability is required for the project.

Analog To Digital Converters (ADC) Selection Notes

Select this component when a dual-channel configuration is required alongside the single-channel ADC09SJ800 or quad-channel ADC09QJ800 variants within the same family. Consider the 555mW per channel power dissipation relative to thermal management capabilities in the target enclosure. Verify that the system requires the specific 9-bit resolution and 800 MSPS speed rather than higher-resolution alternatives like the 12-bit ADC12DJ800.

Analog To Digital Converters (ADC) Part Context

This part belongs to the ADC09xJ800 family, which includes quad, dual, and single-channel versions sharing identical core specifications. All variants utilize the same FCBGA-144 package and feature the same 6GHz input bandwidth and JESD204C interface. The primary distinction between the family members is the number of independent analog input channels available on the die.

Analog To Digital Converters (ADC) Replacement Considerations

ADC09SJ800AAV

Analog To Digital Converters (ADC) FAQ

What is the maximum baud-rate supported by the JESD204C interface?

The device supports a maximum SerDes baud-rate of 17.16Gbps.

How does the device handle high-order harmonics?

The ADC core utilizes an internal dither mechanism specifically designed to reduce high-order harmonics.

Can the device generate its own sampling clock?

Yes, it includes an optional internal sampling clock generation feature with a PLL and VCO operating between 7.2 GHz and 8.2 GHz.