ADC1010S065HN/C1,5

Analog To Digital Converters (ADC) Overview

The ADC1010S065HN/C1 is a single-channel 10-bit Analog-to-Digital Converter (ADC) from NXP Semiconductors, operating at a maximum sampling rate of 65 Msps. It utilizes a pipelined architecture with output error correction to ensure zero missing codes across the full operating range. The device is powered by a single 3 V analog supply and supports flexible digital output logic levels ranging from 1.8 V to 3.3 V via a separate digital supply. Key performance metrics include a Signal-to-Noise Ratio (SNR) of 62 dBFS and a Spurious-Free Dynamic Range (SFDR) of 86 dBc. It features an integrated Serial Peripheral Interface (SPI) for configuration and programmable full-scale input voltage ranges.

Analog To Digital Converters (ADC) Feature Summary

• Single 10-bit pipelined ADC core with guaranteed zero missing codes
• Sample rates up to 65 Msps with SNR of 62 dBFS and SFDR of 86 dBc
• Flexible digital outputs supporting CMOS or LVDS Double Data Rate (DDR) standards
• Integrated SPI interface for register programming and control
• Programmable full-scale input voltage range from 1 V to 2 V peak-to-peak

Analog To Digital Converters (ADC) Applications

• Wireless and wired broadband communications
• Portable instrumentation
• Spectral analysis
• Imaging systems
• Ultrasound equipment
• Software defined radio

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific suffix HN/C1 corresponds to the HVQFN40 package (SOT618-1) as listed in the ordering information table. Confirm that the '065' designation aligns with the 65 Msps sampling rate requirement for your application. Ensure compatibility with the 3 V analog supply and appropriate digital supply voltage (1.8 V to 3.3 V) during procurement planning.

Analog To Digital Converters (ADC) Selection Notes

Select this component when a 10-bit resolution and 65 Msps throughput are sufficient for the target signal bandwidth. Consider the HVQFN40 package constraints if PCB space is limited. Evaluate the need for LVDS DDR versus CMOS outputs based on noise immunity requirements and downstream receiver capabilities. Verify that the 600 MHz input bandwidth exceeds the highest frequency component of the analog signal to be digitized.

Analog To Digital Converters (ADC) Part Context

The ADC1010S065HN/C1 belongs to the ADC1010S series, which includes variants with higher sampling rates such as 80 Msps, 105 Msps, and 125 Msps. These devices share pin compatibility with the ADC1410S, ADC1210S, and ADC1413S/ADC1213S series families, facilitating potential upgrades or design reuse within NXP's data converter portfolio.

Analog To Digital Converters (ADC) Replacement Considerations

Public documentation confirms pin compatibility with the ADC1410S, ADC1210S, and ADC1413S series. Direct substitution requires verifying that the alternative part number matches the required sampling rate, resolution, and package type (HVQFN40).

Analog To Digital Converters (ADC) FAQ

What is the maximum sampling rate for the ADC1010S065 variant?

The ADC1010S065 variant operates at a maximum sampling rate of 65 Msps.

Can the ADC1010S support both CMOS and LVDS outputs?

Yes, the device supports both CMOS and Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) digital output standards, selectable via the SPI interface or control pins.

How is the full-scale input voltage range configured?

The full-scale input voltage range is programmable between 1 V (p-p) and 2 V (p-p) using the internal reference via SPI or external connections to the SENSE and VREF pins.