CY29352AXI

Clock Generators, PLLs, Frequency Synthesizers Overview

The CY29352AXI is a low voltage, high performance 200 MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. It features an LVCMOS reference clock input and provides 11 outputs partitioned into three banks (A, B, C) with configurable dividers allowing output-to-input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. The device operates at 2.5 V or 3.3 V, supports split supply voltages, and delivers up to ±2% maximum output duty cycle variation. It includes Spread Aware technology, output enable/disable control, and pin compatibility with MPC9352 and MPC952.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Configurable frequency division ratios via internal dividers across three output banks
• Integrated Phase Locked Loop (PLL) with bypass mode for flexible clock routing
• Spread Aware technology for electromagnetic interference reduction
• LVCMOS compatible inputs and outputs supporting series or parallel termination

Clock Generators, PLLs, Frequency Synthesizers Applications

• High-speed clock distribution networks
• System-on-Chip (SoC) clocking architectures
• Server and storage system timing solutions
• Telecommunications equipment synchronization

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the ordering suffix 'X' confirms the Industrial temperature range (-40 °C to +85 °C). Confirm the package type is the 32-pin TQFP (7 × 7 × 1.4 mm). Ensure the component is lead-free as per the current Infineon/Cypress product flow specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when a zero-delay buffer with multiple configurable output frequencies is required. Ensure the application supports the 2.5 V or 3.3 V supply rails and requires LVCMOS logic levels. Verify that the 32-pin TQFP package fits the board layout constraints.

Clock Generators, PLLs, Frequency Synthesizers Part Context

Originally developed by Cypress Semiconductor Corporation, this part is now part of the Infineon Technologies portfolio. The datasheet retains the original Cypress branding and document numbering (38-07476 Rev. *F). Infineon continues to support existing ordering part numbers without functional changes.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The datasheet explicitly states pin compatibility with the MPC9352 and MPC952 models. These parts may serve as direct replacements in existing designs requiring identical footprint and electrical characteristics.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What are the available output-to-input frequency ratios?

The device supports ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3 through its configurable internal dividers.

How does the PLL bypass mode function?

When the PLL_EN# pin is HIGH, the PLL is disabled, and the reference clock directly feeds the output dividers in a fully static mode.

What is the maximum output-output skew specification?

The maximum output-to-output skew within a bank is specified as 125 ps.