ISPLSI 3320-70LQ

Complex Programmable Logic Devices Overview

The ispLSI 3320-70LQ is a high-density Complex Programmable Logic Device (CPLD) from Lattice Semiconductor, utilizing E2CMOS technology. It features 14,000 PLD gates, 480 registers, and 160 universal I/O pins within a 208-pin PQFP package. The device supports a maximum operating frequency of 70 MHz with a typical propagation delay of 15 ns. Key architectural elements include 40 Twin Generic Logic Blocks (Twin GLBs), a Global Routing Pool (GRP), and ten Output Routing Pools (ORP). It offers 5V in-system programmability via ISP or IEEE 1149.1 Boundary Scan protocols.

Complex Programmable Logic Devices Feature Summary

• High-density logic architecture with 14,000 PLD gates and 480 registers.
• 160 universal I/O pins with configurable slew rate control to minimize switching noise.
• Supports 5V In-System Programmability (ISP) using Lattice ISP or IEEE 1149.1 Boundary Scan.
• Features five dedicated clock input pins for synchronous and asynchronous clocking.

Complex Programmable Logic Devices Applications

• Complex glue logic integration in digital systems.
• State machine implementation requiring high-speed global interconnect.
• Address decoding and fast counter applications utilizing wide input gating.
• Reconfigurable system designs leveraging non-volatile reprogrammability.

Complex Programmable Logic Devices Procurement Notes

All devices in the ispLSI 3320 family, including the ISPLSI 3320-70LQ, are officially discontinued as per Product Change Notification (PCN) #09-10 issued by Lattice Semiconductor. Verification of current availability should focus on obsolete stock or secondary market sources, as original manufacturing has ceased.

Complex Programmable Logic Devices Selection Notes

Select the ispLSI 3320-70LQ for designs requiring 160 I/Os and high-density logic in a 208-pin PQFP package. The -70 speed grade provides a 70 MHz maximum frequency with 15 ns propagation delay. Ensure compatibility with 5V supply voltages and TTL-compatible signal levels. Consider pin compatibility with the ispLSI 3160 if migration from lower density devices is required.

Complex Programmable Logic Devices Part Context

The ispLSI 3320 belongs to the ispLSI 3000 series of high-density CPLDs. It combines the ease of use of traditional PLDs with the flexibility of field-programmable gate arrays. The device architecture emphasizes complete inter-connectivity through its Global Routing Pool, allowing flexible pin placement and enhanced pin locking capabilities for complex board layouts.

Complex Programmable Logic Devices Replacement Considerations

As the ispLSI 3320-70LQ is discontinued, direct replacements must be sourced from obsolete inventory or alternative manufacturers. No official Lattice successor part numbers are listed in the provided datasheet for this specific legacy component. Designers should evaluate modern CPLD families for equivalent I/O counts and logic density.