MC74AC373DWR2

Latches Overview

The MC74AC373DWR2G is an octal transparent latch with three-state outputs manufactured by onsemi. It operates within a supply voltage range of 2.0 V to 6.0 V and features eight D-type latches in a single package. The device utilizes a SOIC-20W surface-mount package. Propagation delays are specified at 13.5 ns maximum at 3.3 V and 9.5 ns maximum at 5.0 V. Quiescent supply current is limited to 80 µA maximum, while outputs can source or sink up to 24 mA.

Latches Feature Summary

• Contains eight D-type latches with transparent data capture when Latch Enable is HIGH
• Features three-state outputs controlled by Output Enable for bus interfacing
• Provides high drive capability with outputs sourcing and sinking 24 mA

Latches Applications

• Bus organized system applications
• Data storage and buffering
• Bus interfacing

Latches Procurement Notes

Verify the complete part number includes the 'G' suffix for lead-free compliance. Confirm the 'DW' suffix corresponds to the SOIC-20W package. Ensure the 'R2' designation matches the required tape and reel shipping format. Check moisture sensitivity level requirements against your manufacturing process capabilities.

Latches Selection Notes

Select this component for designs requiring multiple latched channels with bus-compatible outputs. The AC series offers wider operating voltage ranges compared to standard logic families. Verify that the propagation delay specifications meet the timing requirements of your specific application circuit.

Latches Part Context

This device belongs to the MC74AC373 family of octal transparent latches. It is functionally compatible with other industry-standard octal latches but offers specific performance characteristics defined by the AC logic series. The datasheet also covers the MC74ACT373 variant which provides TTL-compatible inputs.

Latches Replacement Considerations

MC74AC373DTR2G (TSSOP-20 package)

Latches FAQ

How does the Latch Enable input affect data transparency?

When the Latch Enable (LE) input is HIGH, the latches are transparent, meaning data on the Dn inputs passes directly to the outputs. When LE transitions LOW, the data present at the setup time is latched.

What controls the three-state output mode?

The Output Enable (OE) input controls the three-state outputs. When OE is LOW, the outputs are active. When OE is HIGH, the outputs enter a high impedance state regardless of the latch state.