PI6CB33601ZLAIEX

Clock Buffers, Drivers Overview

The PI6CB33601ZLAIEX is a very low power 6-output PCIe clock buffer manufactured by Diodes Incorporated. It features an on-chip PLL and differential HCSL outputs with integrated 100Ω termination, eliminating the need for external resistors. The device supports input frequencies of 50MHz, 100MHz, 125MHz, and 133.33MHz via SMBus configuration. Operating at a nominal 3.3V supply (3.135V to 3.465V), it provides individual output enables and programmable slew rates. Packaged in a 40-lead 5x5mm TQFN, it meets PCIe Gen1 through Gen5 jitter requirements.

Clock Buffers, Drivers Feature Summary

• Six differential low-power HCSL outputs with built-in 100Ω on-chip termination
• On-chip PLL supporting 50MHz, 100MHz, 125MHz, and 133.33MHz inputs
• Individual active-low output enable pins for each channel
• SMBus interface for configuring frequency, slew rate, amplitude, and impedance

Clock Buffers, Drivers Applications

• PCIe Gen1/Gen2/Gen3/Gen4/Gen5 clock distribution
• Ethernet applications requiring 50MHz, 125MHz, or 133.33MHz clocks
• Spread spectrum clocking systems

Clock Buffers, Drivers Procurement Notes

Verify the ZLA package suffix corresponds to the 40-contact TQFN form factor. Confirm the 'E' suffix indicates lead-free and green compliance. Ensure the 'X' suffix matches the required tape and reel orientation for automated assembly processes.

Clock Buffers, Drivers Selection Notes

Select this component when board space is limited due to its integrated termination, which removes the requirement for 24 external resistors. Use the SMBus capability if dynamic adjustment of output slew rates or amplitudes is necessary during operation. Ensure the system requires differential HCSL signaling compatible with the specified voltage levels.

Clock Buffers, Drivers Part Context

This part belongs to the PI6CB33 series of clock buffers from Diodes Incorporated. It is specifically designed as a slave-only device that utilizes a proprietary PLL architecture to achieve ultra-low jitter performance suitable for high-speed serial interfaces like PCIe.

Clock Buffers, Drivers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Verify pinout compatibility and electrical specifications before considering alternative vendors.

Clock Buffers, Drivers FAQ

How is the SMBus address configured?

The SMBus address is latched on the SADR_TRI pin upon the first assertion of the PD# signal.

What is the default output termination value?

The default on-chip output termination (ZOUT) is 100Ω, though it can be adjusted via SMBus registers.

Can the device operate without the PLL enabled?

Yes, the BW_SEL_TRI pin allows selection of PLL bypass mode, where the device passes the input clock directly to the outputs.