PI6CG330440AZUDIEX-13R

Clock Generators, PLLs, Frequency Synthesizers Overview

The PI6CG330440AZUDIEX-13R is a 19-output PCIe 5.0/6.0 clock generator manufactured by Diodes Incorporated, housed in a 100-contact, 8 x 8 mm UQFN (ZUD) package. It operates on a 3.3V supply voltage and accepts a 25MHz crystal or XO/TCXO/OCXO input. The device provides seven dedicated 100MHz outputs, three dedicated 25MHz outputs, and nine selectable multiplexable outputs capable of driving either 25MHz or 100MHz signals. Outputs utilize 85Ω differential drivers with on-chip termination. Key specifications include PCIe 6.0 common clock RMS jitter below 22fs, programmable spread spectrum capabilities, and SMBus-configurable addresses.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Supports Intel's CK440Q specification for compliant clock generation.
• Integrates on-chip termination to eliminate external resistors and simplify layout.
• Features individual output enable pins for granular power management.
• Includes Platform Time Input and Output pins for frequency locking across devices.

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1 through Gen 6 system designs
• Intel CK440Q compliant motherboard architectures
• High-performance server and networking equipment

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details and tape-and-reel quantities. Ensure that any additional characters in the part number do not indicate alternate configurations or specialized automotive qualifications before finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when a high-density clock solution with integrated termination is required for PCIe 5.0 or 6.0 platforms. Consider the availability of both dedicated and multiplexable outputs to optimize pin count. Verify that the 3.3V supply voltage aligns with the target system's power rails and that the UQFN package dimensions fit the PCB footprint constraints.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This model belongs to the PI6CG330440A series of low-jitter clock generators designed specifically for next-generation PCI Express standards. The family focuses on reducing board complexity through built-in termination while maintaining strict timing accuracy required for high-speed data transmission interfaces.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Consult the manufacturer's cross-reference documentation for verified substitute part numbers. Ensure that any replacement maintains the same 19-output configuration, UQFN package type, and PCIe compliance levels to guarantee functional equivalence without requiring schematic modifications.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How does the Side-Band Interface (SBI) control output enabling?

The SBI uses a shift/load mechanism where 20 bits are shifted into a register via SBI_IN and SBI_CLK, then latched by SHFT_LD#. All three enable methods—OE# pins, SMBus bits, and SBI—must be active for an output to run.

What is the function of the PFT_IN and PFT_OUT pins?

These pins allow different CK440 compliant devices to frequency lock their 25MHz clocks to a single time base. If PFT_IN is present, the local 25MHz locks to it; otherwise, it sources from the local crystal.

Can the multiplexable outputs drive both 25MHz and 100MHz signals?

Yes, the nine selectable MXCK outputs can be configured via the MXCK_SEL_100# pin to drive either 25MHz or 100MHz signals depending on the system requirement.