AD7827BR

Overview

The AD7827BR is an 8-bit, single-channel analog-to-digital converter (ADC) featuring a half-flash architecture and a maximum throughput of 1 MSPS. It operates from a single 3 V or 5 V supply with an input range of 0 V to 2 V or 0 V to 2.5 V, respectively. The device integrates a track-and-hold amplifier, a 2.5 V reference with 2% tolerance, and a serial interface compatible with DSPs. Key electrical parameters include a conversion time of 420 ns, acquisition time of 200 ns, SNR of 48 dB min, INL/DNL of ±0.5 LSB max, and power dissipation of 30 mW max at normal operation.

Feature Summary

• Integrates a track-and-hold amplifier and on-chip 2.5 V reference for simplified system design.
• Features automatic power-down functionality controlled by the CONVST pin state to optimize energy efficiency.
• Provides a three-wire serial interface optimized for direct connection to popular DSPs without external logic.

Applications

• Direct interfacing with TMS320C5x and ADSP-21xx digital signal processors.
• Real-time data acquisition systems requiring high-speed sampling.
• Subsampling applications utilizing input frequencies up to 10 MHz.

Procurement Notes

Verify the specific package variant, as the BR suffix denotes the SOIC-8 option while BN indicates Plastic DIP. Confirm that the B version meets the required industrial temperature range of -40°C to +105°C. Ensure the ordering documentation matches the exact part number to avoid confusion with other series members like the AD7825 or AD7829.

Selection Notes

Select this component when a single-channel, low-power ADC with integrated reference and track-and-hold is required. The choice between 3 V and 5 V operation dictates the analog input voltage span. Consider the automatic power-down mode if average power consumption must be minimized below the standard 30 mW active level.

Part Context

The AD7827 belongs to Analog Devices' family of high-speed, low-power sampling ADCs. It utilizes a half-flash architecture to achieve 8-bit resolution with fast conversion times. This model is designed for applications where space and power are constrained, offering a compact solution compared to discrete track-and-hold and ADC combinations.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Verify compatibility with existing designs before considering alternative models within the manufacturer's portfolio.

FAQ

How does the AD7827 determine its analog input voltage range?

An on-chip VDD detector circuit automatically sets the input range. It detects 5 V operation when VDD exceeds 4.1 V (0 V to 2.5 V range) and 3 V operation when VDD falls below 3.8 V (0 V to 2 V range).

What is the mechanism for automatic power-down?

The state of the CONVST pin is sampled approximately 530 ns after the falling edge of the CONVST pulse. If CONVST is low at this point, the device powers down; it powers up again on the next rising edge of CONVST.

How is the serial data output synchronized?

The RFS (Receive Frame Sync) signal goes logic low on the first rising edge of SCLK after conversion ends. Data bits are shifted out on subsequent rising edges of SCLK, and DOUT enters high impedance after the eighth bit.