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ADSD3500BCBZRL is listed in the Specialized ICS range at ChipApex. The manufacturer field lists Analog Devices Inc.. Its product description is IC IMAGE SIGNL PROCESSOR 81WLCSP. Review the specifications below when checking this part for your BOM.
The ADSD3500BCBZRL is a Time-of-Flight (ToF) Depth Image Signal Processor designed for Analog Devices ToF imagers. It processes raw phase frames to generate radial depth, active brightness, and confidence data. The device supports full-depth processing at 640 × 512 resolution up to 90 FPS and partial depth processing at 1024 × 1024 resolution up to 30 FPS. It integrates an ARM Cortex-M33 processor for data flow control and on-chip SRAM for frame buffering. Power supplies include 1.8 V I/O and 0.8 V core voltages.
Verify the specific suffix BCBZRL against the manufacturer's official documentation to confirm package type and tape & reel configuration. Ensure compatibility with the required MIPI CSI-2 interfaces and power supply specifications (1.8 V I/O, 0.8 V core). Confirm operating temperature range requirements of -25°C to +85°C match the application environment.
Select this component when a dedicated hardware-accelerated solution for ToF depth processing is required. It is suitable for applications needing high-resolution depth maps at significant frame rates. Consider the integrated ARM Cortex-M33 for system control needs. Verify interface compatibility with the host system via MIPI CSI-2 and serial control buses.
The ADSD3500 serves as a specialized ISP for Analog Devices' Time-of-Flight products, such as the ADTF3175 and ADSD3030. It handles the computation of depth, active brightness, and confidence data using dedicated hardware, reducing the load on main processors. This allows for low-power operation in compact form factors like the 3.47 mm × 3.47 mm WLCSP.
No public confirmed substitute part numbers are available in the provided documentation. Consult Analog Devices for potential alternatives if this specific model is unavailable.
It supports full-depth processing at 640 × 512 resolution and partial depth processing at 1024 × 1024 resolution.
Data flow is controlled by the integrated ARM Cortex-M33 processor.
It uses a 4-lane MIPI CSI-2 receiver interface and a 2-lane MIPI CSI-2 transmitter interface, both supporting 2.5 Gbps per lane.
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