Codecs AK4688EN product image

AK4688EN

  • Description:INTEGRATED CIRCUIT
  • Series:-

SKU:e313a22db79e Category: Brand:

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AK4688EN is listed in the Codecs range at ChipApex. The manufacturer field lists Asahi Kasei Microdevices/AKM. Its product description is INTEGRATED CIRCUIT. Review the specifications below when checking this part for your BOM.

Codecs specifications for AK4688EN

  • Description:INTEGRATED CIRCUIT
  • Series:-
  • Mfr:Asahi Kasei Microdevices/AKM
  • Package:Tape & Reel (TR)
  • Type:Stereo Audio
  • Data Interface:I2C, Serial
  • Resolution (Bits):24 b
  • Sigma Delta:Yes
  • S/N Ratio, ADCs / DACs (db) Typ:83 / 95
  • Dynamic Range, ADCs / DACs (db) Typ:99 / 105
  • Voltage - Supply, Analog:3V ~ 3.6V
  • Voltage - Supply, Digital:3V ~ 3.6V
  • Operating Temperature:-20°C ~ 85°C (TA)
  • Mounting Type:Surface Mount
  • Package / Case:36-VFQFN Exposed Pad
  • Supplier Device Package:36-QFN (6x6)
  • Grade:-
  • Qualification:-

Codecs datasheet and documents for AK4688EN

AK4688EN

Codecs Overview

The AK4688EN is an asynchronous stereo audio CODEC featuring integrated ADC and DAC blocks with 24-bit resolution. It supports sampling rates up to 192 kHz for the DAC and 48 kHz for the ADC. The device operates on a single 3.0V to 3.6V supply, utilizing an internal charge pump to generate negative voltage for capless line I/O, delivering a typical 2Vrms output. Key electrical specifications include an ADC dynamic range of 99 dB and a DAC dynamic range of 105 dB. It includes two serial audio interfaces (PORT1 and PORT2) supporting I2S and other formats, housed in a 36-pin QFN package.

Codecs Feature Summary

  • Asynchronous operation capability for independent ADC and DAC clock domains
  • Capless line input/output architecture enabled by an internal charge pump circuit
  • Dual serial audio interfaces supporting master and slave modes with multiple data formats
  • Integrated digital filters including linear phase anti-aliasing and de-emphasis filters

Codecs Applications

  • Digital recording systems
  • Digital television (DTV)
  • Blu-ray recorders
  • Home theater systems

Codecs Procurement Notes

Verify the specific ordering suffix EN against the manufacturer's current datasheet to confirm pin compatibility and temperature range. Ensure the design accounts for the required external capacitors for the charge pump circuit and reference voltage stability across the specified operating temperature range.

Codecs Selection Notes

Select this component when high-resolution 24-bit audio conversion is required with asynchronous clocking flexibility. It is suitable for designs needing capless analog outputs to reduce external component count. Verify that the system clock requirements align with the supported MCLK ratios for the desired sampling rates.

Codecs Part Context

The AK4688EN belongs to the Asahi Kasei Microdevices audio interface IC family. It is designed as a standalone stereo codec solution. Similar models in the portfolio may offer multi-channel configurations or different packaging options, but the AK4688EN specifically targets stereo applications with high dynamic range performance.

Codecs Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Cross-referencing requires consulting official manufacturer substitution guides or equivalent technical specifications from other vendors.

Codecs FAQ

How is the negative voltage for the analog I/O generated?

The AK4688EN uses an internal charge pump circuit powered by the DVDD supply to generate a negative voltage (CVEE), eliminating the need for external negative power supplies or AC-coupling capacitors at the line inputs and outputs.

What control methods are supported for configuration?

The device supports both hardware control via dedicated pins (PDN1, PDN2, MSN, etc.) and I2C-bus control. The mode is selected using the I2C pin, where 'H' enables I2C control and 'L' enables hardware control.

Can the ADC and DAC operate independently?

Yes, the AK4688EN supports asynchronous operation. The ADC (PORT1) and DAC (PORT2) have separate clock inputs (MCLK1/MCLK2, LRCK1/LRCK2, BICK1/BICK2) and can run at different sampling rates without requiring phase synchronization between them.

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