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MCP4232-104E/UN is listed in the Digital Potentiometers range at ChipApex. The manufacturer field lists Microchip Technology. Its product description is IC DGT POT 100KOHM 129TAP 10MSOP. Review the specifications below when checking this part for your BOM.
The MCP4232-104E/UN is a dual-channel digital potentiometer IC featuring volatile memory and an SPI serial interface. It provides two independent rheostat configurations with a nominal resistance (R_AB) of 100 kΩ and ±20% tolerance. The device offers 7-bit resolution, providing 128 discrete taps for precise adjustment. Operating within a supply voltage range of 1.8V to 5.5V, it supports high-voltage tolerant digital inputs up to 12.5V. The component utilizes a 10-pin MSOP package and operates across an extended temperature range from -40°C to +125°C.
Verify the specific ordering suffix against official Microchip documentation to confirm package type and temperature grade. Ensure that system designs account for the volatile nature of the wiper memory, as settings are lost upon power loss. Confirm compatibility with the host controller's SPI voltage levels given the high-voltage input tolerance specifications.
Select this model when dual independent variable resistors are required without non-volatile storage needs. The 100 kΩ value suits applications requiring moderate impedance levels. Verify that the 1.8V minimum supply voltage meets the lowest system rail requirements. Consider the 10-pin MSOP footprint constraints during PCB layout planning.
This component belongs to the MCP413X/415X/423X/425X family of single and dual SPI digital potentiometers. The '42' prefix indicates a dual resistor network configuration, while '3' denotes 7-bit resolution. The '-104' suffix specifies the 100 kΩ resistance value, and '/UN' identifies the MSOP surface-mount package variant.
Direct functional substitutes within the same family include other MCP423x variants with different resistance values or packages. Cross-family replacements require verification of pinout compatibility and SPI protocol alignment.
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