SI5348A-D06323-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5348A-D06323-GM is a network synchronizer clock and jitter cleaner from Skyworks Solutions. It integrates three independent DSPLLs within a single monolithic IC, supporting flexible SyncE, IEEE 1588, and SETS architectures. The device features ultra-low jitter of 100 fs typ (12 kHz to 20 MHz) and meets ITU-T G.8273.2 T-BC, G.8262 EEC Options 1 & 2, G.812 Type III/IV, G.813 Option 1, and Telcordia GR-1244/GR-253 Stratum-3/3E standards. It operates with an input frequency range up to 750 MHz for differential clocks and generates output frequencies up to 718.5 MHz differentially or 250 MHz in LVCMOS. Powered by VDD at 1.8 V ±5% and VDDA at 3.3 V ±5%, it functions within a temperature range of –40 to +85 °C in a 64-Lead 9x9 QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Three independent DSPLLs support flexible SyncE, IEEE 1588, and SETS architectures
• Ultra-low jitter performance of 100 fs typ (12 kHz to 20 MHz)
• Programmable jitter attenuation bandwidth per DSPLL ranging from 0.001 Hz to 4 kHz
• Digitally controlled oscillator (DCO) mode provides precise timing adjustment for 1588 clock steering

Clock Generators, PLLs, Frequency Synthesizers Applications

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to ensure compatibility with required pre-programmed configurations. Confirm that the component meets RoHS-6 compliance and lead-free requirements for your assembly process. Check for any recent product change notices regarding pinout or electrical specifications before finalizing procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when high-frequency synthesis flexibility and ultra-low jitter are critical for network synchronization applications. Ensure the design accommodates the required external crystal (48-54 MHz) and reference clock inputs (TCXO/OCXO). Verify that the serial interface configuration supports the necessary loop bandwidth settings and DCO modes for the target synchronization standard.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5348 family of network synchronizers. The 'A' designation indicates the grade capable of output frequencies up to 718.5 MHz, distinguishing it from the 'B' grade limited to 350 MHz. The 'D' signifies the Rev D datasheet revision, while the numerical sequence represents a factory pre-programmed configuration assigned via ClockBuilder Pro software.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

SI5348A-D-GM

Clock Generators, PLLs, Frequency Synthesizers FAQ

How does the Si5348 handle holdover mode?

When the selected input clock becomes invalid, the DSPLL automatically enters Holdover Mode. It uses an averaged input clock frequency stored in historical data to minimize phase and frequency disturbance, with the final accuracy dependent on the external TCXO/OCXO reference.

What is the purpose of the DCO mode?

The Digitally Controlled Oscillator (DCO) mode allows precise timing adjustment to 1 ppt/step. It is primarily used in IEEE 1588 (PTP) applications where a processor controls the DCO to close the timing loop between master and slave nodes based on recovered timestamps.

Can the input selection be automated?

Yes, input selection can be made manually through register control or automatically using an internal state machine. In automatic mode, the DSPLL selects the valid input with the highest configured priority, monitoring for Loss of Signal (LOS) and Out of Frequency (OOF).