SI5367C-C-GQ

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5367C-C-GQ is a µP-programmable precision clock multiplier utilizing Silicon Laboratories' DSPLL technology. It accepts four differential or single-ended clock inputs ranging from 10 to 710 MHz and generates five frequency-multiplied outputs spanning 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device supports any-frequency synthesis without external VCXO or loop filter components. It operates on a single 1.8 V, 2.5 V, or 3.3 V supply and features digitally programmable PLL loop bandwidths between 150 kHz and 1.3 MHz. Configuration is managed via I²C or SPI interfaces.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates virtually any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Provides low jitter clock outputs with jitter generation as low as 0.6 ps rms within the 50 kHz to 80 MHz bandwidth.
• Integrates an internal loop filter with selectable digital loop bandwidth to optimize jitter performance at the application level.
• Supports four clock inputs with manual or automatically controlled switching and includes LOS alarm outputs.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/OC-192 STM-16/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Wireless base stations
• Data converter clocking

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and temperature grade. Confirm RoHS compliance status and lead times directly with authorized distributors or the manufacturer. Ensure the design utilizes the correct supply voltage range of 1.8 V, 2.5 V, or 3.3 V as specified in the electrical characteristics.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when precise clock multiplication without jitter attenuation is required. Verify that the input frequency range of 10 to 710 MHz matches the source clocks. Check if the output frequency requirements up to 1.4 GHz are supported by the specific speed grade. Consider the power dissipation limits if multiple LVPECL or CMOS outputs are enabled simultaneously.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5367 belongs to the Si53xx family of precision clock multipliers based on DSPLL technology. It is designed for high-performance timing applications requiring flexible frequency synthesis. The device eliminates the need for external analog components typically found in traditional PLL solutions, offering a highly integrated approach for generating multiple clock domains from fewer reference sources.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The datasheet explicitly states the Si5367 is not recommended for new designs. Designers should evaluate the Si533x family of products as the suggested alternative for new implementations.