SI5369D-C-GQR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5369D-C-GQR is a jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts four clock inputs from 2 kHz to 710 MHz and generates five outputs ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device operates on a single 1.8 V, 2.5 V, or 3.3 V supply within an ambient temperature range of -40°C to +85°C. It features digitally programmable loop bandwidths between 4 Hz and 525 Hz, integrated on-chip voltage regulation, and supports I2C or SPI interfaces for configuration.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Provides ultra-low jitter performance with generation as low as 300 fs rms in the 12 kHz to 20 MHz band.
• Supports manual or automatically controlled hitless switching and phase build-out among four clock inputs.
• Includes SONET frame sync switching, regeneration capabilities, and support for ITU G.709 and custom FEC ratios.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10G FC line cards
• ITU G.709 and custom FEC line cards
• Wireless repeaters and wireless backhaul systems
• Data converter clocking

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific suffix 'GQR' against the manufacturer's official ordering guide to confirm package type and tape-and-reel specifications. Confirm RoHS compliance status and lead times directly with Skyworks Solutions or authorized distributors prior to procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when sub 1 ps rms jitter performance is required for high-speed timing applications. Ensure the design accommodates the 100-pin TQFP package dimensions and verify that the chosen output signal formats (LVPECL, LVDS, CML, CMOS) align with power dissipation limits at the selected supply voltage.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5369 belongs to the Si536x product family designed for high-speed communications and data center equipment. It complements other jitter attenuators by offering up to 18 clock outputs in some variants, though this specific model provides five outputs. It addresses timing needs for 400G/800G networks and AI infrastructure requiring ultra-low jitter margins.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Evaluate alternative Skyworks Si536x family members based on output count and frequency requirements if direct replacement is necessary.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the Si5369?

The device generates outputs ranging from 2 kHz to 945 MHz generally, with select frequencies capable of reaching 1.4 GHz.

Does the Si5369 require external components for loop filtering?

No, the device integrates the loop filter and eliminates the need for external VCXO and loop filter components due to its digitally programmable PLL architecture.

How does the device handle input clock transitions?

It supports hitless switching between input clocks compliant with GR-253-CORE and GR-1244-CORE, minimizing phase transient propagation to less than 200 ps typically.