XC6129C25C9R-G

Supervisors Overview

The XC6129C25C9R-G is a voltage detector manufactured by Torex Semiconductor Ltd, designed for monitoring power supply levels in electronic circuits. It features an adjustable delay time and operates within a supply voltage range of 1.3 V to 6 V. The device provides a low-active CMOS output and includes manual reset functionality. It is housed in a USPN-4 package and supports operation temperatures from -40°C to +85°C.

Supervisors Feature Summary

• Adjustable delay time for customizable reset timing
• Manual reset input capability
• Low quiescent current consumption
• CMOS output structure

Supervisors Applications

• Portable equipment battery monitoring
• Microprocessor system reset circuits
• Memory backup power switching

Supervisors Procurement Notes

Verify the specific threshold voltage code suffix against official datasheets to ensure correct detection level. Confirm package type and reel specifications match design requirements. Check RoHS compliance status for regulatory adherence. Validate operating temperature range suitability for the target environment.

Supervisors Selection Notes

Select this component when a fixed threshold with adjustable delay is required. Ensure the monitored voltage falls within the 1.3 V to 6 V operational range. Consider the USPN-4 package size for space-constrained designs. Verify that the CMOS output drive capability meets downstream logic requirements.

Supervisors Part Context

This part belongs to the XC6129 series of voltage detectors from Torex Semiconductor. The series offers various threshold voltages and package options. It is categorized under supervisory circuits and power management ICs. The product is intended for general-purpose voltage monitoring applications.

Supervisors Replacement Considerations

Check for direct pin-compatible substitutes within the XC6129 family with different threshold codes. Verify equivalent delay adjustment mechanisms and output types. Ensure thermal and electrical specifications match the original design constraints.