ADADC71JD

Analog To Digital Converters (ADC) Overview

The ADADC71JD is a 16-bit hybrid analog-to-digital converter featuring an internal reference and clock. It offers ±0.006% maximum linearity error and supports input ranges of ±2.5 V, ±5 V, ±10 V, 0 to +5 V, 0 to +10 V, and 0 to +20 V. The device operates on ±15 V analog and +5 V digital supplies with typical power consumption of 645 mW. Conversion time is 35 μs typical (50 μs max) for 14 bits. It utilizes parallel logic outputs and is housed in a 32-pin hermetic ceramic DIP package.

Analog To Digital Converters (ADC) Feature Summary

• High-resolution 16-bit conversion using laser-trimmed thin-film components and proprietary monolithic DAC chips.
• Integrated internal reference voltage and clock generator eliminating external component requirements.
• Flexible input scaling supporting multiple bipolar and unipolar voltage ranges via direct connection.
• Parallel TTL-compatible digital outputs with status flag indicating conversion completion.

Analog To Digital Converters (ADC) Applications

• Medical and analytic instrumentation
• Precision measurement for industrial robots
• Automatic test equipment
• Multi-channel data acquisition systems
• Servo-control systems

Analog To Digital Converters (ADC) Procurement Notes

Verify the specific suffix JD against the ordering guide to confirm the ±0.006% linearity specification and commercial temperature range. Ensure the design accommodates the required ±15 V and +5 V supply rails. Confirm that the 32-pin ceramic DIP footprint matches the PCB layout constraints. Check for ESD sensitivity precautions during handling.

Analog To Digital Converters (ADC) Selection Notes

Select the ADADC71KD if a tighter linearity specification of ±0.003% is required. Consider the short cycle capability if lower resolution with faster throughput is sufficient for the application. Evaluate the need for external gain and offset adjustment circuits to minimize drift errors over the operating temperature range.

Analog To Digital Converters (ADC) Part Context

The ADADC71 is part of Analog Devices' high-precision hybrid ADC family. It combines a 16-bit successive-approximation register with a monolithic DAC. The JD variant specifies a maximum linearity error of ±0.006% FSR. It is designed for applications requiring high stability and accuracy without external precision components.

Analog To Digital Converters (ADC) Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The serial output function was discontinued after date code 0120; verify date codes if legacy compatibility is required.

Analog To Digital Converters (ADC) FAQ

What digital output coding does the ADADC71JD use?

It uses complementary straight binary (CSB) for unipolar input ranges and complementary offset binary (COB) for bipolar ranges. Complementary two's complement (CTC) can be obtained by inverting Pin 1 (MSB).

How is the conversion time affected by resolution?

The maximum conversion time is 50 μs for 14 bits. Short cycle capability allows termination after any number of bits, reducing time for lower resolutions (e.g., 35.6 μs for 10 bits).

Are external calibration adjustments necessary?

Initial gain and offset errors are specified at ±0.2% and ±0.1% FSR respectively. External trim circuits using potentiometers can adjust these errors to zero for higher precision.