Complex Programmable Logic Devices EPM7128SLC84-6F product image

EPM7128SLC84-6F

$52.28
  • Description:IC CPLD 128MC 6NS 84PLCC
  • Series:MAX® 7000S

SKU:dc618750482a Category: Brand:

  
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EPM7128SLC84-6F is listed in the Complex Programmable Logic Devices range at ChipApex. The manufacturer field lists Altera. Its product description is IC CPLD 128MC 6NS 84PLCC. Review the specifications below when checking this part for your BOM.

Complex Programmable Logic Devices specifications for EPM7128SLC84-6F

  • Description:IC CPLD 128MC 6NS 84PLCC
  • Series:MAX® 7000S
  • Mfr:Altera
  • Package:Tray
  • Programmable Type:In System Programmable
  • Delay Time tpd(1) Max:6 ns
  • Voltage Supply - Internal:4.75V ~ 5.25V
  • Number of Macrocells:128
  • Number of I/O:68
  • Operating Temperature:0°C ~ 70°C (TA)
  • Mounting Type:Surface Mount
  • Package / Case:84-LCC (J-Lead)
  • Supplier Device Package:84-PLCC (29.31x29.31)
  • Number of Gates:2500
  • Number of Logic Elements/Blocks:8

Complex Programmable Logic Devices datasheet and documents for EPM7128SLC84-6F

EPM7128SLC84-6F

Complex Programmable Logic Devices Overview

The Altera EPM7128SLC84-6F is a Complex Programmable Logic Device (CPLD) belonging to the MAX 7000S family. It features 128 macrocells, 2,500 usable gates, and 68 user I/O pins housed in an 84-pin PLCC package. The device operates at 5.0 V with a maximum pin-to-pin propagation delay of 6 ns and a counter frequency of 147.1 MHz. It supports In-System Programming (ISP) via a JTAG interface using a constant algorithm, indicated by the 'F' suffix.

Complex Programmable Logic Devices Feature Summary

  • MAX 7000S architecture with 128 macrocells and 2,500 usable gates
  • In-system programmability (ISP) via IEEE Std. 1149.1 JTAG interface
  • Constant algorithm programming for compatibility with specific test equipment
  • Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1

Complex Programmable Logic Devices Applications

  • Address decoding and bus control logic
  • Signal processing and timing control circuits
  • Interface bridging between TTL and CMOS standards
  • Industrial control system logic implementation

Complex Programmable Logic Devices Procurement Notes

Verify that the 'F' suffix corresponds to devices tested with the constant ISP algorithm, which is required for use with in-circuit testers that do not support adaptive algorithms. Confirm the 84-pin PLCC package type matches the design footprint. Check component lifecycle status as this series may be discontinued.

Complex Programmable Logic Devices Selection Notes

Select this model when 5.0 V operation and JTAG-based ISP are required. The -6 speed grade provides a 6 ns delay suitable for moderate-speed applications. Ensure the design utilizes the constant algorithm programming flow if deployed with legacy ICT equipment. Compare against EPM7128E if ISP functionality is not needed.

Complex Programmable Logic Devices Part Context

This component is part of the Altera MAX 7000 family, based on second-generation MAX architecture and CMOS EEPROM technology. The MAX 7000S variant specifically adds JTAG boundary-scan and in-system programming capabilities to the enhanced features found in the MAX 7000E series.

Complex Programmable Logic Devices Replacement Considerations

Direct replacements include other EPM7128 variants within the MAX 7000S family, such as EPM7128SLC84-7 or EPM7128SLC84-10, provided the speed grade requirements are met. Pin-compatible alternatives from the MAX 7000E series exist but lack ISP functionality.

EPM7128SLC84-6FEPM7128SLC84-6F
$52.28
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