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Product Detailed Parameters
- Description:IC MULTIPLEXER 3 X 2:1 20SOIC
- Series:100LVEL
- Mfr:onsemi
- Package:Bulk
- Type:Multiplexer
- Circuit:3 x 2:1
- Independent Circuits:1
- Current - Output High, Low:-
- Voltage Supply Source:Dual Supply
- Voltage - Supply:±3V ~ 3.8V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:20-SOIC (0.295", 7.50mm Width)
- Supplier Device Package:20-SOIC
- Grade:-
- Qualification:-
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Overview
The MC100LVEL59DWR2 is a 3.3 V triple 2:1 multiplexer with differential outputs, manufactured by onsemi in the 100LVEL series. It operates within a PECL mode range of VCC = 3.0 V to 3.8 V (VEE = 0 V) or an NECL mode range of VCC = 0 V (VEE = −3.0 V to −3.8 V). The device features typical propagation delays of 500 ps and meets EIA/JESD78 latchup specifications. It utilizes a 20-lead SOIC package (DW suffix) and is supplied in tape and reel format containing 1000 units.
Feature Summary
- Supports individual or common select controls for flexible data path management
- Includes internal input pulldown resistors ensuring Q output defaults LOW when inputs are open
- Provides over 2 kV HBM ESD protection capability
- Incorporates temperature compensation for stable performance across operating ranges
Applications
- Data path routing applications
- Random logic circuit implementations
- High-speed signal switching systems
Procurement Notes
Verify that the specific ordering suffix DWR2 corresponds to the tape and reel packaging configuration containing 1000 units per reel. Confirm the presence of the G suffix if lead-free compliance is required, as standard versions may differ in material composition. Ensure power supply connections for all VCC and VEE pins are externally managed to guarantee proper operation.
Selection Notes
Select this component for designs requiring three independent 2:1 multiplexing channels with differential signaling capabilities. Consider the dual-mode voltage support for compatibility with both PECL and NECL logic families. Evaluate the 500 ps propagation delay against system timing requirements to ensure adequate speed for high-frequency data processing tasks.
Part Context
This part belongs to the MC100LVEL59 series of low-voltage ECL multiplexers. It shares functional characteristics with other devices in the 100LVEL family but is distinct in its triple 2:1 configuration and specific pinout arrangement within the 20-lead SOIC package. The series emphasizes high-speed performance and robust environmental stability.
Replacement Considerations
Direct substitutes include the MC100LVEL59DW for tube packaging or the MC100LVEL59DWR2G for lead-free tape and reel variants. Verify pin compatibility and electrical specifications before substituting with other multiplexer models from different manufacturers.
FAQ
How does the device handle open inputs?
Internal input pulldown resistors ensure that the Q output defaults to a LOW state if any inputs are left open or connected to VEE.
What are the valid operating voltage modes?
The device supports PECL mode with VCC between 3.0 V and 3.8 V and VEE at 0 V, or NECL mode with VCC at 0 V and VEE between −3.0 V and −3.8 V.
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