PI6CV855LE

Clock Generators, PLLs, Frequency Synthesizers Overview

The PI6CV855LE is a PLL-based clock driver designed for SSTL_2 DDR SDRAM applications. It operates with AVDD and VDDQ at 2.5V (range 2.3V to 2.7V). The device distributes one differential clock input pair (CLK, CLK) to five differential output pairs (Y0-Y4) and provides one differential feedback pair (FBOUT, FBOUT). Inputs and outputs utilize SSTL_2 levels. The maximum operating frequency is 167 MHz, with an application frequency up to 134 MHz. Key timing parameters include a maximum cycle-to-cycle jitter of 57 ps, period jitter of 57 ps, and half-period jitter of 101 ps. Input/output slew rates are between 0.2 and 1.0 V/ns. The component is housed in a 28-pin TSSOP package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Zero-delay buffer architecture synchronizes outputs to the input clock via external feedback pins.
• Optimized for SSTL_2 DDR SDRAM memory systems with differential data input and output levels.
• Supports Spread Spectrum Clocking (SSC) tracking to reduce electromagnetic interference.
• Includes a test bypass mode where strapping AVDD low disables the PLL.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SSTL_2 DDR SDRAM memory subsystems
• Registered DIMM clock distribution
• High-speed digital system clock buffering

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix 'LE' corresponds to the Pb-free and Green packaging variant as documented in the datasheet. Confirm that the 28-pin TSSOP physical dimensions match the target PCB footprint requirements. Ensure supply chain sources provide original manufacturer documentation to validate the component's authenticity and compliance status.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when designing SSTL_2 compliant DDR memory interfaces requiring a single differential input to drive multiple loads. The device supports frequencies up to 167 MHz. Consider the 28-pin TSSOP package constraints. Verify that the system power supplies can maintain the required 2.5V range for both analog and I/O sections.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the PI6CV855 series of PLL clock drivers manufactured by Diodes Incorporated. It is specifically engineered for memory applications using SSTL_2 signaling standards. The LE suffix indicates the lead-free and environmentally friendly packaging configuration available for this specific model.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not provided in the source material.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the PLL bypassed for testing purposes?

The PLL is turned off and bypassed by strapping the Analog Power input (AVDD) low.

What is the maximum operating frequency of the PI6CV855?

The maximum operating frequency is 167 MHz, while the application frequency meets all timing parameters up to 134 MHz.

What voltage levels do the inputs and outputs use?

Both the inputs (CLK, CLK, FBIN, FBIN) and outputs (Yx, Yx, FBOUT, FBOUT) operate at SSTL_2 levels.