SI5330K-A00226-GM

Clock Buffers, Drivers Overview

The SI5330K-A00226-GM is a low-jitter, low-skew clock buffer and level translator manufactured by Skyworks Solutions Inc. It accepts a single-ended input signal and generates four differential LVPECL outputs. The device operates with a core supply voltage of 1.8 V, 2.5 V, or 3.3 V, while the output driver supply (VDDO) is independently set to 2.5 V for this specific configuration. It supports an input frequency range of 5 MHz to 350 MHz. Key electrical characteristics include a typical additive phase jitter of 150 fs RMS (12 kHz–20 MHz), an output-to-output skew of 100 ps maximum, and a typical propagation delay of 2.5 ns.

Clock Buffers, Drivers Feature Summary

• Converts single-ended input to four differential LVPECL outputs
• Low additive jitter: 150 fs RMS typical (12 kHz–20 MHz)
• Independent core (VDD) and output (VDDO) supply voltages
• Glitchless output enable via OEB pin and Loss of Signal (LOS) indicator

Clock Buffers, Drivers Applications

• High-speed clock distribution in telecom line cards
• Clock buffering for Ethernet switches and routers
• SONET/SDH network equipment
• PCI Express 2.0/3.0 interface synchronization

Clock Buffers, Drivers Procurement Notes

Verify that the ordering suffix matches the required input/output format and supply voltage. The 'GM' suffix indicates tube packaging, whereas adding an 'R' specifies tape and reel shipment. Confirm the specific A00226 code corresponds to the 2.5 V LVPECL output configuration with single-ended input before procurement.

Clock Buffers, Drivers Selection Notes

Select this part when a single-ended source must drive multiple LVPECL loads. Ensure the system provides a 2.5 V supply for the VDDO pins to match the output swing requirements. The core VDD can be powered at 1.8 V, 2.5 V, or 3.3 V to optimize power consumption. Verify that the input frequency does not exceed 350 MHz for this specific variant.

Clock Buffers, Drivers Part Context

This component belongs to the Si5330 family of low-jitter clock buffers. The 'K' designation specifically identifies it as a single-ended input to differential output converter. Other variants in the family support differential inputs or different output formats such as LVDS, HCSL, CMOS, SSTL, and HSTL.

Clock Buffers, Drivers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.