SI5335A-B02062-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5335A-B02062-GM is a web-customizable, any-frequency, any-output quad clock generator and buffer. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It features low phase jitter of 0.7 ps RMS, two selectable PLL loop bandwidths (1.6 MHz or 475 kHz), and operates on a single core supply of 1.8, 2.5, or 3.3 V within the –40 to +85 °C temperature range.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Synthesizes four independent, non-integer-related output frequencies up to 350 MHz with 0 ppm frequency error.
• Supports multiple input types: external crystal, CMOS, SSTL/HSTL, and differential signals.
• Configurable output drivers supporting LVPECL, LVDS, CML, HCSL, CMOS, and SSTL/HSTL formats.
• Features low phase jitter (0.7 ps RMS typical) and selectable PLL loop bandwidths (1.6 MHz or 475 kHz).

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock generation
• Ethernet switch and router timing
• Processor and FPGA clocking
• DSL jitter attenuation
• Broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the ordering suffix B02062 against the system requirements. Confirm that the required output frequencies, voltage levels, and control pin assignments match the programmed design. Ensure compatibility with the ClockBuilder Pro utility for any necessary validation of the customized parameters before integration.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when a single device must replace multiple clock generators or buffers with diverse frequency and format requirements. Choose between the 1.6 MHz and 475 kHz loop bandwidth settings based on whether jitter attenuation or faster lock time is prioritized. Ensure the application supports the 24-QFN package dimensions and thermal characteristics specified for the Si5335 family.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5335 family of highly flexible clock generators. The 'A' variant typically denotes specific performance or feature sets within the series, while the suffix indicates a unique factory-programmed configuration. It serves as a drop-in replacement for discrete oscillators and buffers in complex digital systems requiring precise, multi-frequency clock distribution.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct functional replacements require identical factory configurations. Verify pin-to-pin compatibility with the 24-QFN package. Check if alternative Si5335 variants with different suffixes offer the same synthesized frequencies and output formats without requiring hardware changes.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the Si5335?

The Si5335 supports output frequencies up to 350 MHz for LVPECL, LVDS, CML, SSTL, and HSTL formats. HCSL outputs are supported up to 250 MHz, and CMOS outputs up to 200 MHz.

How does the device handle frequency synthesis error?

Using Skyworks' patented MultiSynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of the configuration.

Can the Si5335 operate in both clock generator and buffer modes?

Yes, the device is configurable as either a clock generator using its internal PLL or as a clock buffer device with the PLL bypassed.