SI5342C-B-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5342C-B-GMR is a jitter attenuator and clock multiplier from the Si5342 family, featuring four inputs and two outputs in a 44-QFN package. It supports integer-only frequency synthesis with output frequencies ranging from 0.001 MHz to 1028 MHz. The device achieves ultra-low jitter of 90 fs rms and operates on core voltages of VDD at 1.8 V ±5% and VDDA at 3.3 V ±5%. It accepts differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. The component functions within a temperature range of –40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Combines fourth-generation DSPLL and MultiSynth technologies for any-frequency generation and jitter attenuation
• Supports free-run, synchronous, and holdover modes with automatic or manual input clock switching
• Features fully integrated loop filter and digitally programmable jitter attenuation bandwidth
• Includes in-circuit programmable non-volatile memory for known power-up configuration

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm tape and reel packaging status. Confirm that the 'C' designation aligns with the required integer-only synthesis mode for the target application. Ensure compatibility with the 44-QFN 7x7 mm footprint during PCB layout planning.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when only two output clocks are required alongside four available inputs. The 'C' variant restricts synthesis to integer modes; fractional synthesis requires an 'A' or 'B' variant. Verify that the 1028 MHz maximum output frequency meets system requirements and that the 90 fs rms jitter specification satisfies the noise budget.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D series of jitter attenuating clock multipliers. While the Si5345 offers ten outputs and the Si5344 provides four, the Si5342 specifically delivers two outputs. All variants share identical internal DSPLL and MultiSynth architectures but differ in pin count and I/O capacity.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

SI5342A-D-GMR

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the SI5342C?

The SI5342C supports a maximum output frequency of 1028 MHz.

Does the SI5342C support fractional frequency synthesis?

No, the 'C' suffix indicates that the device supports integer-only frequency synthesis.

How does the device handle input clock failure?

The device automatically enters holdover mode using stored historical frequency data if the selected input clock becomes invalid.