SI5345B-D06732-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-D06732-GMR is a jitter attenuating clock multiplier from the Si5345 family, featuring four inputs and ten outputs. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any combination of output frequencies from any input frequency. The device supports differential inputs up to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 350 MHz for differential formats and 100 Hz to 250 MHz for LVCMOS. It provides ultra-low jitter performance of 90 fs rms and meets ITU-T G.8262 EEC Options 1 and 2. The component operates within a temperature range of -40°C to +85°C and is housed in a 64-QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fractional and integer synthesis modes.
• Features an integrated loop filter and digitally programmable jitter attenuation bandwidth for optimized noise performance.
• Supports hitless input clock switching between fractionally related clocks and glitchless on-the-fly frequency changes.
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the D06732 suffix against the required system specifications. Confirm that the QFN-64 package dimensions and thermal requirements align with the target PCB layout. Ensure compatibility with the I2C or SPI serial interface used by the host controller for operational control.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when ten independent output clocks are required with frequencies capped at 350 MHz. The Si5345B variant is appropriate for applications prioritizing low jitter over the higher frequency capabilities of the Si5345A series. Verify that the available input sources match the supported differential or LVCMOS voltage levels defined in the datasheet.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D family of jitter attenuators. The Si5345 variant specifically offers the highest channel count within the family, providing four inputs and ten outputs in a 64-QFN package. It shares core DSPLL technology with the Si5344 and Si5342 models but distinguishes itself through its expanded output capacity.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5345B-D-GM

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency for the Si5345B variant?

The maximum output frequency for the Si5345B variant is 350 MHz for differential outputs and 250 MHz for LVCMOS outputs.

Does the device support synchronization to gapped input clocks?

Yes, the DSPLL supports locking to gapped input clocks, provided the minimum frequency is 10 MHz with no more than two missing cycles out of every eight.

How is the jitter attenuation bandwidth controlled?

The jitter attenuation bandwidth is digitally programmable via registers, allowing selection from 0.1 Hz to 4 kHz to optimize performance for specific applications.